公开(公告)号：US20190361813A1

公开(公告)日：2019-11-28

申请号：US16437900

申请日：2019-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0897 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F12/0815 ,  G06F12/0862

Abstract: A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

公开(公告)号：US10459843B2

公开(公告)日：2019-10-29

申请号：US15395028

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F12/0846

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

公开(公告)号：US10339057B2

公开(公告)日：2019-07-02

申请号：US15384487

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/312 ,  G06F9/315 ,  G06F15/80 ,  G06F12/02 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F9/32

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

公开(公告)号：US10318293B2

公开(公告)日：2019-06-11

申请号：US14327038

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.

公开(公告)号：US10073696B2

公开(公告)日：2018-09-11

申请号：US15384342

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/0811

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/621

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

公开(公告)号：US09904645B2

公开(公告)日：2018-02-27

申请号：US14530203

申请日：2014-10-31

Applicant: Texas Instruments Incorporated

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/364 ,  H04L12/819 ,  H04L12/801

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

公开(公告)号：US20170308381A1

公开(公告)日：2017-10-26

申请号：US15635409

申请日：2017-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/34 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/34 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

公开(公告)号：US20160124883A1

公开(公告)日：2016-05-05

申请号：US14530203

申请日：2014-10-31

Applicant: Texas Instruments Incorporated

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

Abstract translation: 本发明是总线通信协议。 主设备存储总线信用。 主设备只有在拥有足够数量和类型的总线信用时才可以传输总线事务。 在传输时，主设备减少存储的总线信用的数量。 总线信用量对应于从设备上用于接收总线事务的资源。 如果伴随着适当的信用，从设备必须接收总线交易。 从设备为事务提供服务。 然后从设备传送信用回报。 主设备将相应的信用数量和类型添加到存储量。 从设备准备接受另一个总线事务，并且主设备被重新启用以启动总线事务。 在许多类型的交互中，根据进程的状态，总线代理可以充当主机和从机。

公开(公告)号：US12288069B2

公开(公告)日：2025-04-29

申请号：US18607703

申请日：2024-03-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0875

Abstract: A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.

公开(公告)号：US12223327B2

公开(公告)日：2025-02-11

申请号：US18487186

申请日：2023-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Duc Bui ,  Joseph Zbiciak ,  Reid E. Tatge

IPC: G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.