公开(公告)号：US20240387501A1

公开(公告)日：2024-11-21

申请号：US18782354

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong Chern ,  Yi-An Lai

IPC: H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

公开(公告)号：US11841561B2

公开(公告)日：2023-12-12

申请号：US17379620

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiwei Song ,  Stefan Rusu ,  Chan-Hong Chern ,  Chih-Chang Lin

IPC: G02F1/025 ,  G02F1/225

CPC classification number: G02F1/025 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2201/508 ,  G02F2201/58

Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.

公开(公告)号：US20230231046A1

公开(公告)日：2023-07-20

申请号：US18124490

申请日：2023-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong Chern

IPC: H01L29/778 ,  H03K17/567 ,  H01L27/07 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H03K17/567 ,  H01L27/0727 ,  H01L29/66462

Abstract: Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

公开(公告)号：US20230154912A1

公开(公告)日：2023-05-18

申请号：US17650758

申请日：2022-02-11

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chan-Hong Chern ,  Yi-An Lai

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/83047 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1425

Abstract: A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

公开(公告)号：US11531159B2

公开(公告)日：2022-12-20

申请号：US17212934

申请日：2021-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong Chern ,  Lan-Chou Cho ,  Huan-Neng Chen ,  Min-Hsiang Hsu ,  Feng-Wei Kuo ,  Chih-Chang Lin ,  Weiwei Song ,  Chewn-Pu Jou

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13

Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

公开(公告)号：US20210396930A1

公开(公告)日：2021-12-23

申请号：US17212934

申请日：2021-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong Chern ,  Lan-Chou Cho ,  Huan-Neng Chen ,  Min Hsiang Hsu ,  Feng-Wei Kuo ,  Chih-Chang Lin ,  Weiwei Song ,  Chewn-Pu Jou

IPC: G02B6/122 ,  G02B6/13

Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the second waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

公开(公告)号：US20210193564A1

公开(公告)日：2021-06-24

申请号：US16984297

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiwei Song ,  Chan-Hong Chern ,  Feng-Wei Kuo ,  Lan-Chou Cho ,  Stefan Rusu

IPC: H01L23/52 ,  G02B6/43 ,  H01L31/0232 ,  H01L31/18

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.

公开(公告)号：US11024626B2

公开(公告)日：2021-06-01

申请号：US16576525

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong Chern

IPC: H01L27/088 ,  H01L29/778 ,  H03K17/687 ,  H01L21/8252 ,  H01L29/43 ,  H01L29/66

Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

公开(公告)号：US20140270031A1

公开(公告)日：2014-09-18

申请号：US14164399

申请日：2014-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen (David) Chung ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin

IPC: H04L7/00

CPC classification number: H04L7/0025 ,  H03L7/0812

Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.

Abstract translation: 一些实施例涉及相位插值器。 相位内插器包括控制块，用于提供多个相位插值控制信号，这些相位插值控制信号被共同指示第一时钟和第二时钟之间的相位差。 相位插值控制信号限定不同的相位步长，通过该相位步长第一时钟将被相移以限制相位差。 多个吉尔伯特单元基于多个相位插值控制信号分别提供多个电流电平。 多个电流控制元件从多个吉尔伯特单元调整多个电流电平。 对于不同的相位步长，多个电流水平被不同的量调节。

公开(公告)号：US12124088B2

公开(公告)日：2024-10-22

申请号：US18232319

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiang Hsu ,  Chewn-Pu Jou ,  Chan-Hong Chern ,  Cheng-Tse Tang ,  Yung-Jr Hung ,  Lan-Chou Cho

IPC: G02B6/30

CPC classification number: G02B6/305

Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.