公开(公告)号：US08160098B1

公开(公告)日：2012-04-17

申请号：US12353946

申请日：2009-01-14

Applicant: Anlu Yan ,  Tong Liu ,  Chad Mikkelson ,  Aimin Ding

Inventor： Anlu Yan ,  Tong Liu ,  Chad Mikkelson ,  Aimin Ding

IPC: H04J3/16

CPC classification number: H04L47/522 ,  H04L47/626 ,  H04L47/6275 ,  H04L47/762 ,  H04L47/822

Abstract: In one example, a bandwidth allocation device allocates physical channel bandwidth between local interfaces. Thereafter, at a polling time, the bandwidth allocation device determines whether there is communication activity between each local interface and the physical channel. The bandwidth allocation device can then dynamically reallocate the physical channel bandwidth at the polling time according to the communication activity determinations.

Abstract translation: 在一个示例中，带宽分配设备在本地接口之间分配物理信道带宽。 此后，在轮询时间，带宽分配装置确定每个本地接口与物理信道之间是否存在通信活动。 然后，带宽分配设备可以根据通信活动确定在轮询时间动态地重新分配物理信道带宽。

公开(公告)号：US20110130981A1

公开(公告)日：2011-06-02

申请号：US12956842

申请日：2010-11-30

Applicant: Gholamreza Chaji ,  Joseph Marcel Dionne ,  Yaser Azizi ,  Javid Jaffari ,  Abbas Hormati ,  Tong Liu ,  Stefan Alexander

Inventor： Gholamreza Chaji ,  Joseph Marcel Dionne ,  Yaser Azizi ,  Javid Jaffari ,  Abbas Hormati ,  Tong Liu ,  Stefan Alexander

IPC: G06F19/00 ,  G09G5/10 ,  G01R31/28

CPC classification number: G09G3/006 ,  G01R31/44 ,  G09G3/3233 ,  G09G3/3283 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/029 ,  G09G2320/0295 ,  G09G2320/043 ,  G09G2320/045

Abstract: Methods and systems to provide baseline measurements for aging compensation for a display device are disclosed. An example display system has a plurality of active pixels and a reference pixel. Common input signals are provided to the reference pixel and the plurality of active pixels. The outputs of the reference pixel is measured and compared to the output of the active pixels to determine aging effects. The display system may also be tested applying a first known reference current to a current comparator with a second variable reference current and the output of a device under test such as one of the pixels. The variable reference current is adjusted until the second current and the output of the device under test is equivalent of the first current. The resulting current of the device under test is stored in a look up table for a baseline for aging measurements during the display system operation. The display system may also be tested to determine production flaws by determining anomalies such as short circuits in pixel components such as OLEDs and drive transistors.

Abstract translation: 公开了提供用于显示装置的老化补偿的基线测量的方法和系统。 示例性显示系统具有多个有源像素和参考像素。 公共输入信号被提供给参考像素和多个有源像素。 测量参考像素的输出并将其与有源像素的输出进行比较，以确定老化效应。 还可以使用第二可变参考电流和正在测试的设备的输出（诸如像素之一）将显示系统应用于当前比较器的第一已知参考电流。 调整可变参考电流，直到第二个电流和被测器件的输出等于第一个电流。 在显示系统操作期间，被测器件的结果电流存储在查询表中，用于老化测量的基线。 也可以通过确定诸如OLED和驱动晶体管等像素部件中的短路的异常来测试显示系统来确定生产缺陷。

公开(公告)号：US07720160B1

公开(公告)日：2010-05-18

申请号：US11639656

申请日：2006-12-14

Applicant: James L. Gorecki ,  Tong Liu

Inventor： James L. Gorecki ,  Tong Liu

IPC: H04B14/06 ,  H04L7/00 ,  H03M1/20

CPC classification number: H04B14/062 ,  H03L7/0812 ,  H03L7/093 ,  H03M3/50 ,  H03M7/3026 ,  H04L7/0025 ,  H04L7/033

Abstract: A method and apparatus for converting a high precision digital word into a high precision analog signal is disclosed. A sigma delta modulator applies a digital input signal to a dither signal to generate a combined signal for sampling. A digital-to-analog converter quantizes the combined signal. An analog filter provides a cutoff at a bandwidth of interest to remove out of band quantization noise and signals. An I transfer function and a Q transfer function can be coupled between the sigma delta modulator and the digital-to-analog converter for mapping of the combined signal. The apparatus can also include a phase interpolator for receiving the output signal and outputting a clock recovery phase.

Abstract translation: 公开了一种用于将高精度数字字转换成高精度模拟信号的方法和装置。 Σ-Δ调制器将数字输入信号施加到抖动信号以产生用于采样的组合信号。 数模转换器对组合信号进行量化。 模拟滤波器在感兴趣的带宽上提供截止以去除带外量化噪声和信号。 可以在Σ-Δ调制器和数 - 模转换器之间耦合I传递函数和Q传递函数，用于映射组合信号。 该装置还可以包括用于接收输出信号并输出​​时钟恢复阶段的相位插值器。

公开(公告)号：US07342416B2

公开(公告)日：2008-03-11

申请号：US11561705

申请日：2006-11-20

Applicant: Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

Inventor： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC: H03K19/0177

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Abstract translation: 一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。 第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US20080005414A1

公开(公告)日：2008-01-03

申请号：US11418888

申请日：2006-05-05

Applicant: Tong Liu ,  Yung-Chin Fang

Inventor： Tong Liu ,  Yung-Chin Fang

IPC: G06F13/38

CPC classification number: H04L67/025 ,  G06F3/023 ,  H04L67/36 ,  H04L67/40

Abstract: A keyboard, video monitor and mouse (KVM) Universal Serial Bus (USB) Internet protocol (IP) server interface pod (SIP) allows access to selected ones of a plurality of servers by a remotely located keyboard, video monitor and mouse. In addition, remote mounting of a USB device to the selected server is also possible. A digital KVM USB switch may be used for routing the remotely located keyboard, video monitor, mouse and USB device to the KVM USB IP SIP. The digital KVM USB switch also is coupled to a KVM USB IP interface. The KVM USB IP interface is located with and connected to the remotely located keyboard, video monitor, mouse and USB device. The KVM USB IP interface may be coupled to the digital KVM USB switch over a local area network (LAN), wide area network (WAN), or Internet.

Abstract translation: 键盘，视频监视器和鼠标（KVM）通用串行总线（USB）互联网协议（IP）服务器接口盒（SIP）允许通过位于远程的键盘，视频监视器和鼠标来访问多个服务器中的选定的服务器。 此外，还可以将USB设备远程安装到所选择的服务器。 数字KVM USB开关可用于将远程位置的键盘，视频监视器，鼠标和USB设备路由到KVM USB IP SIP。 数字KVM USB开关也耦合到KVM USB IP接口。 KVM USB IP接口位于远程位置的键盘，视频监视器，鼠标和USB设备上。 KVM USB IP接口可以通过局域网（LAN），广域网（WAN）或互联网耦合到数字KVM USB交换机。

公开(公告)号：US20070273874A1

公开(公告)日：2007-11-29

申请号：US11438698

申请日：2006-05-23

Applicant: Jian Xu ,  Tong Liu

Inventor： Jian Xu ,  Tong Liu

IPC: G01N21/88 ,  G01B11/24

CPC classification number: G01B11/0608 ,  G01B11/306

Abstract: A method of dynamically imaging, calibrating and measuring bump height and coplanarity of a plurality of bumps on a surface is disclosed. The method includes illuminating the plurality of bumps with multispectral light from at least one light source, and receiving light of a first wavelength at an imaging device such that a top view image of at least a portion of the plurality of bumps is captured. The light of the first wavelength is reflected off the plurality of bumps at a first angle from the surface. Light of a second wavelength is received at the imaging device such that at least one oblique side view image of at least a portion of the plurality of bumps is captured. The light of the second wavelength is reflected off the plurality of bumps at a second angle from the surface. The captured images are processed to determine absolute bump height and coplanarity. A corresponding apparatus is also disclosed.

Abstract translation: 公开了一种动态地成像，校准和测量表面上的多个凸块的凸起高度和共面性的方法。 该方法包括用来自至少一个光源的多光谱光照射多个凸起，以及在成像装置处接收第一波长的光，使得捕获多个凸块的至少一部分的俯视图像。 第一波长的光从表面以第一角度从多个凸起反射出来。 在成像装置处接收第二波长的光，使得捕获多个凸起的至少一部分的至少一个倾斜侧视图。 第二波长的光从表面以第二角度从多个凸起反射。 捕获的图像被处理以确定绝对凸起高度和共面性。 还公开了相应的装置。

公开(公告)号：US20070075742A1

公开(公告)日：2007-04-05

申请号：US11561705

申请日：2006-11-20

Applicant: Sheng Feng ,  Jung-Cheun Lien ,  Eddy Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

Inventor： Sheng Feng ,  Jung-Cheun Lien ,  Eddy Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Abstract translation: 一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。 第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US07157938B2

公开(公告)日：2007-01-02

申请号：US11335396

申请日：2006-01-18

Applicant: Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

Inventor： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Abstract translation: 一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。 第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US20060114024A1

公开(公告)日：2006-06-01

申请号：US11335396

申请日：2006-01-18

Applicant: Sheng Feng ,  Jung-Cheun Lien ,  Eddy Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

Inventor： Sheng Feng ,  Jung-Cheun Lien ,  Eddy Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Abstract translation: 一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。 第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US20050215520A1

公开(公告)日：2005-09-29

申请号：US10514184

申请日：2003-05-09

Applicant: Yunqing Liu ,  Xiving Liu ,  Wei Liu ,  Tong Liu

Inventor： Yunqing Liu ,  Xiving Liu ,  Wei Liu ,  Tong Liu

IPC: A61K9/02 ,  A61K9/00 ,  A61K9/08 ,  A61K9/12 ,  A61K9/14 ,  A61K9/19 ,  A61K9/20 ,  A61K9/48 ,  A61K31/045 ,  A61K31/138 ,  A61K31/167 ,  A61K31/337 ,  A61K31/357 ,  A61K31/366 ,  A61K31/40 ,  A61K31/426 ,  A61K31/43 ,  A61K31/4422 ,  A61K31/495 ,  A61K31/496 ,  A61K31/519 ,  A61K31/522 ,  A61K31/566 ,  A61K31/573 ,  A61K31/585 ,  A61K31/635 ,  A61K31/7048 ,  A61K31/7052 ,  A61K38/00 ,  A61K47/08 ,  A61K47/40 ,  A61K47/48 ,  A61P9/00 ,  A61P11/12 ,  A61P11/14 ,  A61P25/04 ,  A61P29/00 ,  A61P31/04 ,  A61P31/10 ,  A61P33/06 ,  A61P35/00 ,  A61P37/06 ,  C08B37/00 ,  C08B37/16 ,  A61K31/724 ,  C08B30/18

CPC classification number: A61K9/0019 ,  A61K47/40 ,  A61K47/6951 ,  B82Y5/00 ,  C08B37/0012 ,  C08B37/0015

Abstract: The present invention relates to a process of preparing a water-soluble complex of water-insoluble or sparingly-soluble organic medicines and beta-cyclodextrin derivatives: a. dissolving successively or simultaneously the organic medicines and the beta-cyclodextrin derivatives in organic solvent(s) at certain mole ratio or mass ratio in the presence of suitable amount of water; b. removing the organic solvent from the solution of the step a to obtain aqueous solution of the organic medicine and beta-cyclodextrin derivative; and c. removing water from the aqueous solution to obtain the complex of the organic medicine and beta-cyclodextrin derivative. The invention also provides a sterile water-soluble complex of water-insoluble or sparingly-soluble organic medicines and beta-cyclodextrin derivatives. A fully-water-soluble complex can be prepared from any water-insoluble or sparingly-soluble organic medicines or other organic compounds according to the present invention. Thus, appreciably convenient means are provided for industrial uses of such organic medicine preparations and of other organic compounds.

Abstract translation: 本发明涉及一种制备水不溶性或微溶性有机药物和β-环糊精衍生物的水溶性络合物的方法：a。 在适当量的水存在下，有机药物和β-环糊精衍生物相继或同时地以某些摩尔比或质量比在有机溶剂中溶解; b。 从步骤a的溶液中除去有机溶剂，得到有机药物和β-环糊精衍生物的水溶液; 和c。 从水溶液中除去水分，得到有机药物和β-环糊精衍生物的复合物。 本发明还提供了水不溶性或微溶性有机药物和β-环糊精衍生物的无菌水溶性复合物。 完全水溶性的络合物可以由根据本发明的任何水不溶性或微溶性有机药物或其它有机化合物制备。 因此，为这种有机药物制剂和其它有机化合物的工业用途提供了方便的手段。