公开(公告)号：US20200035680A1

公开(公告)日：2020-01-30

申请号：US16594054

申请日：2019-10-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Wei Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yan-Jou Chen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L27/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.

公开(公告)号：US09929154B2

公开(公告)日：2018-03-27

申请号：US14541085

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Wei-Heng Hsu ,  Yu-Ming Lin ,  Ya-Ru Yang

IPC: H01L27/085 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8258 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

公开(公告)号：US09793296B2

公开(公告)日：2017-10-17

申请号：US15296027

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

公开(公告)号：US09508799B2

公开(公告)日：2016-11-29

申请号：US14469566

申请日：2014-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract translation: 公开了一种用于制造半导体器件的衬底的方法。 该方法包括以下步骤：提供第一硅层; 在所述第一硅层上形成介电层; 将第二硅层接合到介电层; 去除所述第二硅层的一部分和所述介电层的一部分以限定所述第一硅层上的第一区域和第二区域，其中所述第二硅层和所述介电层的剩余部分位于所述第二区域上; 以及在所述第一硅层的所述第一区上形成外延层，其中所述外延层和所述第二硅层包含相同的晶体取向。

公开(公告)号：US20160141288A1

公开(公告)日：2016-05-19

申请号：US14541085

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Wei-Heng Hsu ,  Yu-Ming Lin ,  Ya-Ru Yang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/205 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

Abstract translation: 鳍状结构及其形成方法。 该方法包括提供具有第一鳍结构和第二鳍结构的衬底。 接下来，在基板上形成绝缘材料层。 然后，去除第一鳍片结构的一部分以形成第一凹部。 接下来，在第一凹部中依次形成第一缓冲层和第一沟道层。 接下来，去除第二鳍结构的一部分，以形成第二凹部。 然后，顺序地在第二凹部中形成第二缓冲层和第二沟道层，其中第二缓冲层与第一缓冲层不同。

公开(公告)号：US08823109B2

公开(公告)日：2014-09-02

申请号：US13736951

申请日：2013-01-09

Applicant: United Microelectronics Corp.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US08822297B2

公开(公告)日：2014-09-02

申请号：US13748279

申请日：2013-01-23

Applicant: United Microelectronics Corp.

Inventor： Tsung-Han Lee ,  Cheng-Tung Huang ,  Yi-Han Ye

IPC: H01L21/8249

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 在衬底上形成至少一个栅极结构，其中栅极结构包括栅极导电层和设置在栅极导电层上的硬掩模层。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域，其中栅极导电层被硬掩模层覆盖。 执行去除硬掩模层以暴露栅极导电层的表面的工艺。 执行第二注入工艺以在衬底中形成口袋掺杂区域，其中栅极导电层未被硬掩模层覆盖。

公开(公告)号：US20140206170A1

公开(公告)日：2014-07-24

申请号：US13748279

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Han Lee ,  Cheng-Tung Huang ,  Yi-Han Ye

IPC: H01L29/66

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 在衬底上形成至少一个栅极结构，其中栅极结构包括栅极导电层和设置在栅极导电层上的硬掩模层。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域，其中栅极导电层被硬掩模层覆盖。 执行去除硬掩模层以暴露栅极导电层的表面的工艺。 执行第二注入工艺以在衬底中形成口袋掺杂区域，其中栅极导电层未被硬掩模层覆盖。

公开(公告)号：US20250120094A1

公开(公告)日：2025-04-10

申请号：US18504143

申请日：2023-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yan-Jou Chen ,  Chien-Yu Ko ,  Cheng-Tung Huang

IPC: H10B61/00

Abstract: A memory device includes a first memory cell, a second memory cell, a word line, a bit line, a first source line and a second source line. The first memory cell includes a control terminal, a data terminal and a source terminal. The first memory cell includes a control terminal, a data terminal and a source terminal. The word line is coupled to the control terminal of the first memory cell and the control terminal of the second memory cell. The bit line is coupled to the data terminal of the first memory cell and the data terminal of the second memory cell. The first source line is coupled to the source terminal of the first memory cell for receiving a first source voltage. The second source line is coupled to the source terminal of the second memory cell for receiving a second source voltage.

公开(公告)号：US20240422988A1

公开(公告)日：2024-12-19

申请号：US18352269

申请日：2023-07-14

Applicant: United Microelectronics Corp.

Inventor： Cheng-Tung Huang ,  Yanjou Chen ,  Chien-Yu Ko

IPC: H10B61/00

Abstract: Provided is a semiconductor structure including a circuit layer, an island-shaped conductive layer, a MRAM cell, a bit line and a conductive via. The circuit layer is disposed on a substrate. The island-shaped conductive layer is disposed on the circuit layer. The MRAM cell is disposed between the island-shaped conductive layer and the circuit layer, and is electrically connected to the island-shaped conductive layer and the circuit layer. The bit line is disposed on the island-shaped conductive layer. The conductive via is disposed between the bit line and the island-shaped conductive layer. The island-shaped conductive layer is in contact with a top surface of the MRAM cell.