公开(公告)号：US20240057488A1

公开(公告)日：2024-02-15

申请号：US18382055

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

公开(公告)号：US11621271B2

公开(公告)日：2023-04-04

申请号：US17177164

申请日：2021-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L21/28 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20220262808A1

公开(公告)日：2022-08-18

申请号：US17706577

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20220262806A1

公开(公告)日：2022-08-18

申请号：US17177164

申请日：2021-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11387337B2

公开(公告)日：2022-07-12

申请号：US17134131

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

公开(公告)号：US20170084622A1

公开(公告)日：2017-03-23

申请号：US14856577

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.

公开(公告)号：US12295144B2

公开(公告)日：2025-05-06

申请号：US18602040

申请日：2024-03-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H10B43/35 ,  H10D30/01 ,  H10D30/69 ,  H10D64/01

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate disposed on a substrate, a dielectric layer and two charge trapping layers, wherein the dielectric layer is disposed between the substrate and the memory gate, and the two charge trapping layers are disposed at two opposite sides of the memory gate, wherein each of the charge trapping layers comprises an L-shape cross-sectional profile, and two selective gates disposed on the substrate, thereby constituting a two bit memory cell, wherein a top surface of each selective gate is higher than a top surface of the memory gate.

公开(公告)号：US11956966B2

公开(公告)日：2024-04-09

申请号：US17706577

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L29/72 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/35

CPC classification number: H10B43/35 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11127752B2

公开(公告)日：2021-09-21

申请号：US16798126

申请日：2020-02-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang ,  Chun-Sung Huang

IPC: H01L21/00 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/792 ,  H01L21/765 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

公开(公告)号：US20210233924A1

公开(公告)日：2021-07-29

申请号：US17229848

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L27/11568 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49 ,  H01L21/027 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3213 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.