公开(公告)号：US12102014B2

公开(公告)日：2024-09-24

申请号：US18376437

申请日：2023-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

公开(公告)号：US20240049608A1

公开(公告)日：2024-02-08

申请号：US18381627

申请日：2023-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device includes a substrate, a first MTJ structure, a second MTJ structure, an interconnection structure including a first metal interconnection and a second metal interconnection disposed on and contacting the first metal interconnection, a fifth metal interconnection, and a sixth metal interconnection. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction. The fifth metal interconnection and the sixth metal interconnection are disposed under and contact the first MTJ structure and the second MTJ structure, respectively. The fifth metal interconnection includes a barrier layer and a metal layer disposed on the barrier layer. A length of the first MTJ structure in the first horizontal direction is greater than a length of the metal layer in the first horizontal direction.

公开(公告)号：US11818965B2

公开(公告)日：2023-11-14

申请号：US17867702

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H10B61/00 ,  H10N50/80 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

公开(公告)号：US20220367565A1

公开(公告)日：2022-11-17

申请号：US17345806

申请日：2021-06-11

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H01L27/22 ,  H01L23/522 ,  H01L23/528 ,  H01L43/12 ,  H01L43/02

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US20210028351A1

公开(公告)日：2021-01-28

申请号：US17064607

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

公开(公告)号：US20180331193A1

公开(公告)日：2018-11-15

申请号：US16044581

申请日：2018-07-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Yun-Tzu Chang ,  Wei-Ning Chen ,  Wei-Ming Hsiao ,  Chia-Chang Hsu ,  Kuo-Chih Lai ,  Yang-Ju Lu ,  Yen-Chen Chen ,  Chun-Yao Yang

IPC: H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L29/49 ,  H01L29/06 ,  H01L27/092 ,  H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/42356 ,  H01L21/02183 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

公开(公告)号：US20170323950A1

公开(公告)日：2017-11-09

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/285 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US09691704B1

公开(公告)日：2017-06-27

申请号：US15175299

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia-Chang Hsu ,  Nien-Ting Ho ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Yang-Ju Lu ,  Wei-Ming Hsiao ,  Wei-Ning Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

公开(公告)号：US09400435B2

公开(公告)日：2016-07-26

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F7/20 ,  G03F9/00 ,  G05B19/18 ,  G03F1/42

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。

公开(公告)号：US20160126194A1

公开(公告)日：2016-05-05

申请号：US14533108

申请日：2014-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Teng-Chin Kuo ,  En-Chiuan Liou

IPC: H01L23/544 ,  H01L21/311 ,  G01B11/00

CPC classification number: H01L21/311 ,  G01B11/002 ,  G03F7/70633 ,  G03F7/70683

Abstract: The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped.

Abstract translation: 本发明提供一种测量标记结构，包括多个内部图案，内部图案沿着第一方向布置，外部图案位于围绕内部图案的位置，外部图案是矩形框形。