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    Vertically mountable interposer assembly and method
    21.
    发明授权
    Vertically mountable interposer assembly and method 失效
    垂直安装的插件，组装和方法

    公开(公告)号：US06191474B1

    公开(公告)日：2001-02-20

    申请号：US09001406

    申请日：1997-12-31

    Applicant: Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

    Inventor： Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

    IPC: H01L2312

    CPC classification number: H05K3/301 ,  H01L23/32 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2924/00

    Abstract: A support assembly for mounting a semiconductor device vertically relative to a carrier substrate. The support assembly includes an interposer to which the semiconductor device is attached. The support assembly also includes traces carried on the interposer, which electronically connect the semiconductor device to contacts on the interposer. The contacts are disposed along a single edge of the interposer. The invention also includes an alignment device for releaseably mounting the support assembly. The alignment device, which mounts to a carrier substrate, includes one or more receptacles. As a support assembly is inserted into a receptacle, the alignment device establishes an electrical connection between the contacts and corresponding terminals on the carrier substrate. The assembly may also include a cover that attaches to the top of the alignment device and biases the interposer against the carrier substrate.

    Abstract translation: 一种用于相对于载体基板垂直安装半导体器件的支撑组件。 支撑组件包括插入件，半导体器件附接到该插入器。 支撑组件还包括承载在插入器上的迹线，其将半导体器件电连接到插入器上的触点。 触点沿着插入器的单个边缘设置。 本发明还包括用于可释放地安装支撑组件的对准装置。 安装到载体基板的对准装置包括一个或多个插座。 当支撑组件插入到插座中时，对准装置在触点和载体基板上的相应端子之间建立电连接。 组件还可以包括附接到对准装置的顶部并将插入件偏压抵靠载体基板的盖。

    Semiconductor device including combed bond pad opening, assemblies and methods
    22.
    发明授权
    Semiconductor device including combed bond pad opening, assemblies and methods 有权
    半导体器件包括精梳接合焊盘开口，组件和方法

    公开(公告)号：US6144560A

    公开(公告)日：2000-11-07

    申请号：US464992

    申请日：1999-12-16

    Applicant: Warren M. Farnworth ,  Walter L. Moden ,  Larry D. Kinsman

    Inventor： Warren M. Farnworth ,  Walter L. Moden ,  Larry D. Kinsman

    IPC: H01L23/32 ,  H01L23/48 ,  H05K7/10

    CPC classification number: H01L23/32 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/3011

    Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.

    Abstract translation: 一种半导体器件，包括靠近其边缘的接合焊盘和外涂层。 外涂层在每个接合焊盘周围形成凹口。 外涂层可以由可光成像的材料例如可光成像的环氧树脂形成。 本发明还包括将半导体器件垂直地固定在载体衬底上的对准装置。 对准装置包括对应于半导体器件的接合焊盘的中间导电元件。 在将半导体器件插入到对准装置中时，凹口有助于键合焊盘与其对应的中间导电元件的对准。 中间导电元件在半导体器件和载体衬底之间建立电连接。

    Semiconductor device socket, assembly and methods
    23.
    发明授权
    Semiconductor device socket, assembly and methods 有权

    公开(公告)号：US6088237A

    公开(公告)日：2000-07-11

    申请号：US207646

    申请日：1998-12-08

    Applicant: Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

    Inventor： Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

    IPC: H01R12/89 ,  H05K7/10

    CPC classification number: H05K7/1007 ,  H01R12/89

    Abstract: A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased position. After placement of the intermediate conductive elements into an insertion position, a semiconductor device may be inserted into a receptacle of the socket with minimal insertion force. Movement of the member to a biased position facilitates biasing of the intermediate conductive elements against a bond pad of the semiconductor device. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate. A first embodiment of the socket includes a member which moves transversely relative to the remainder of the socket. In a second embodiment of the socket, the member moves vertically relative to the socket body.

    Die paddle heat sink with thermal posts
    24.
    发明授权
    Die paddle heat sink with thermal posts 有权
    带散热片的模具散热片

    公开(公告)号：US6061242A

    公开(公告)日：2000-05-09

    申请号：US257567

    申请日：1999-02-25

    Applicant: David J. Corisis ,  Walter L. Moden

    Inventor： David J. Corisis ,  Walter L. Moden

    IPC: H01L23/495 ,  H05K3/30 ,  H05K7/20

    CPC classification number: H05K3/303 ,  H01L23/49568 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613

    Abstract: A semiconductor device having a die paddle and a die disposed on the die paddle. The die paddle serves as a heat dissipation device and the die paddle is partially and/or fully encapsulated by a package body. Thermal posts extend from the die paddle to direct heat from the semiconductor device to a printed circuit board and further provide stability and alignment during placement of the semiconductor device on the printed circuit board.

    Abstract translation: 一种半导体器件，具有裸片和芯片上的裸片。 管芯焊盘用作散热装置，并且管芯焊盘部分地和/或完全被封装主体封装。 散热柱从模板延伸，以将热量从半导体器件引导到印刷电路板，并且在将半导体器件放置在印刷电路板上时进一步提供稳定性和对准。

    Tie bar over chip lead frame design
    27.
    发明授权
    Tie bar over chip lead frame design 失效
    领带超薄芯片引线框设计

    公开(公告)号：US5539251A

    公开(公告)日：1996-07-23

    申请号：US390606

    申请日：1995-02-17

    Applicant: Robert E. Iverson ,  Walter L. Moden

    Inventor： Robert E. Iverson ,  Walter L. Moden

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16195

    Abstract: A "leads over chip" lead frame design is disclosed which can be used with a conventional die having leads located at the periphery. The inventive design uses an elongated tie bar which extends from one side of the lead frame to the other, across the die. The die is attached to the bottom of the tie bar, then the bond pads are wire bonded to the lead fingers. The lead fingers of the inventive lead frame do not extend over the top of the die, but are positioned in close proximity to allow for short bond wires. The die and a portion of the lead fingers are encapsulated, and the tie bars are severed to separate them from the lead frame. The invention allows the advantages of a leads over die configuration with a conventional die having bond pads located at the periphery. Therefor, a single die can be manufactured which can be used either with the inventive lead frame for a plastic package, or with a ceramic package.

    Abstract translation: 公开了一种“引线过芯片”引线框设计，其可以与具有位于外围的引线的常规裸片一起使用。 本发明的设计使用细长的连接杆，其从引线框架的一侧延伸到另一侧，穿过模具。 模具附接到连杆的底部，然后将接合焊盘引线接合到引线指。 本发明引线框架的引线指不延伸超过模具的顶部，而是位于紧密接近以允许短接合线。 模具和引线指的一部分被封装，并且连接条被切断以将它们与引线框架分开。 本发明允许使用具有位于周边的接合垫的常规管芯的引线超过管芯配置的优点。 因此，可以制造单个模具，其可以用于本发明的用于塑料封装的引线框架，或者与陶瓷封装件一起使用。

    Vertical surface mount assembly and methods
    29.
    发明授权
    Vertical surface mount assembly and methods 有权
    垂直表面安装组件及方法

    公开(公告)号：US07227261B2

    公开(公告)日：2007-06-05

    申请号：US10648164

    申请日：2003-08-26

    Applicant: Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

    Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

    IPC: H01L23/34

    CPC classification number: H05K3/301 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the semiconductor device may be exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. The alignment device may secure the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

    Abstract translation: 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 可以暴露半导体器件的至少一部分。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 对准装置可以使垂直安装的半导体器件封装相对于载体衬底垂直地固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。

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