公开(公告)号：US09818724B2

公开(公告)日：2017-11-14

申请号：US14561164

申请日：2014-12-04

Applicant: ams AG

Inventor： Jochen Kraft ,  Martin Schrems ,  Franz Schrank

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/14 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24146 ,  H01L2224/24147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/85 ,  H01L2224/85005 ,  H01L2224/9222 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/207

Abstract: The interposer-chip-arrangement comprises an interposer (1), metal layers arranged above a main surface (10), a further metal layer arranged above a further main surface (11) opposite the main surface, an electrically conductive interconnection (7) through the interposer, the interconnection connecting one of the metal layers and the further metal layer, a chip (12) arranged at the main surface or at the further main surface, the chip having a contact pad (15), which is electrically conductively connected with the interconnection, a dielectric layer (2) arranged above the main surface with the metal layers embedded in the dielectric layer, a further dielectric layer (3) arranged above the further main surface with the further metal layer embedded in the further dielectric layer, and an integrated circuit (25) in the interposer, the integrated circuit being connected with at least one of the metal layers (5).

公开(公告)号：US09684074B2

公开(公告)日：2017-06-20

申请号：US15101893

申请日：2014-12-03

Applicant: ams AG

Inventor： Franz Schrank ,  Eugene G. Dierschke ,  Martin Schrems

IPC: H01L33/00 ,  G01S17/02 ,  H01L31/0203 ,  H01L33/52 ,  H01L31/0216 ,  H01L33/48 ,  G01S7/481 ,  H01L25/16 ,  H01L31/12 ,  H01L31/14 ,  H01L27/144 ,  H01L31/02 ,  H01L31/0232 ,  H01L31/173

CPC classification number: G01S17/026 ,  G01S7/4813 ,  H01L25/167 ,  H01L27/1443 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02164 ,  H01L31/02165 ,  H01L31/02325 ,  H01L31/02327 ,  H01L31/125 ,  H01L31/14 ,  H01L31/167 ,  H01L31/173 ,  H01L33/483 ,  H01L33/52 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An optical sensor arrangement, in particular an optical proximity sensor arrangement comprises a three-dimensional integrated circuit further comprising a first layer comprising a light-emitting device, a second layer comprising a light-detector and a driver circuit. The driver circuit is electrically connected to the light-emitting device and to the light-detector to control the operation of the light-emitting device and the light-detector. A mold layer comprising a first light-barrier between the light-emitting device and the light-detector configured to block light from being transmitted directly from the light-emitting device to the light-detector.

公开(公告)号：US09543245B2

公开(公告)日：2017-01-10

申请号：US14441165

申请日：2013-09-23

Applicant: ams AG

Inventor： Franz Schrank ,  Martin Schrems

IPC: G01N27/12 ,  H01L23/528 ,  H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/528 ,  G01N27/128 ,  H01L21/50 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The semiconductor device comprises a substrate (1) of semiconductor material with a front side (4) and an opposite rear side (7), a wiring layer (5) at the front side (4), a further wiring layer (8) at the rear side (7), and a through-substrate via (3) connecting the wiring layer (5) and the further wiring layer (8). A hot plate (24) is arranged on or in the substrate, and a sensor layer (21) is arranged in the vicinity of the hot plate. A mold compound (14) is arranged on the rear side (7) above the substrate (1), a cavity (17) is formed in the mold compound (14) to accommodate the sensor layer (21), and the cavity (17) is covered with a membrane (15).

Abstract translation: 半导体器件包括具有前侧（4）和相对的后侧（7）的半导体材料的衬底（1），在前侧（4）处的布线层（5），另一布线层（8） 背面（7）和连接布线层（5）和另一布线层（8）的贯穿基板通孔（3）。 热板（24）布置在基板上或基板上，传感器层（21）布置在热板附近。 在基板（1）上方的后侧（7）上配置有模具化合物（14），在模具化合物（14）中形成空腔（17），以容纳传感器层（21）和空腔 ）被膜（15）覆盖。

公开(公告)号：US08969193B2

公开(公告)日：2015-03-03

申请号：US13956274

申请日：2013-07-31

Applicant: ams AG

Inventor： Jochen Kraft ,  Franz Schrank ,  Martin Schrems

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.

Abstract translation: 在具有包括金属平面（5）的金属间电介质（4）和具有绝缘层（2）的相对后表面（15）的主表面（14）上设置半导体基板（1）和导电连接垫 （7）。 在金属间电介质上施加蚀刻停止层（6），以防止在随后的方法步骤期间去除金属平面之上的金属间电介质。 具有侧壁（3）和底部（13）的开口（9）通过连接垫上方的基板从主表面形成。 通过产生并随后部分去除电介质层（11），在侧壁上形成侧壁间隔物（10）。 绝缘层从底部移除以露出连接垫的一个区域。 金属层被施加在开口中并且被提供用于通过基底的互连。