公开(公告)号：US10389306B2

公开(公告)日：2019-08-20

申请号：US15690115

申请日：2017-08-29

Applicant: pSemi Corporation

Inventor： Poojan Wagh ,  Kashish Pal ,  Robert Mark Englekirk ,  Tero Tapio Ranta ,  Keith Bargroff ,  Simon Edward Willard

IPC: H03F1/22 ,  H03F1/02 ,  H03F3/193

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

公开(公告)号：US20190158031A1

公开(公告)日：2019-05-23

申请号：US16250889

申请日：2019-01-17

Applicant: pSemi Corporation

Inventor： Jonathan James Klaren ,  David Kovac ,  Eric S. Shapiro ,  Christopher C. Murphy ,  Robert Mark Englekirk ,  Keith Bargroff ,  Tero Tapio Ranta

IPC: H03F1/22 ,  H03F1/30 ,  H03F3/24 ,  H03F3/195 ,  H03F3/213 ,  H03F3/193 ,  H03F1/56

CPC classification number: H03F1/223 ,  H03F1/301 ,  H03F1/56 ,  H03F3/193 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/105 ,  H03F2200/165 ,  H03F2200/18 ,  H03F2200/21 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/243 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/306 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/399 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/498 ,  H03F2200/555 ,  H03F2200/61 ,  H03F2200/78

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

公开(公告)号：US20180337146A1

公开(公告)日：2018-11-22

申请号：US15600579

申请日：2017-05-19

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L23/60 ,  H01L27/12 ,  H01L29/786 ,  H01L23/66 ,  H01L23/552 ,  H01L29/10 ,  H03K17/687

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

公开(公告)号：US20240094757A1

公开(公告)日：2024-03-21

申请号：US18359513

申请日：2023-07-26

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

IPC: G05F3/26 ,  G05F3/24 ,  H03M1/66

CPC classification number: G05F3/262 ,  G05F3/242 ,  H03M1/66 ,  H03M1/742

Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

公开(公告)号：US20230387864A1

公开(公告)日：2023-11-30

申请号：US18322166

申请日：2023-05-23

Applicant: pSemi Corporation

Inventor： Jonathan James Klaren ,  David Kovac ,  Eric S. Shapiro ,  Christopher C. Murphy ,  Robert Mark Englekirk ,  Keith Bargroff ,  Tero Tapio Ranta

IPC: H03F1/22 ,  H03F3/195 ,  H03F3/213 ,  H03F3/24 ,  H03F1/30 ,  H03F1/56 ,  H03F3/193

CPC classification number: H03F1/223 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F1/301 ,  H03F1/56 ,  H03F3/193 ,  H03F2200/165 ,  H03F2200/21 ,  H03F2200/225 ,  H03F2200/243 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/306 ,  H03F2200/391 ,  H03F2200/399 ,  H03F2200/42 ,  H03F2200/48 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/498 ,  H03F2200/555 ,  H03F2200/61 ,  H03F2200/78 ,  H03F2200/102 ,  H03F2200/105 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

公开(公告)号：US11507125B2

公开(公告)日：2022-11-22

申请号：US16989435

申请日：2020-08-10

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

IPC: G05F3/26 ,  H03M1/66 ,  G05F3/24 ,  H03M1/74

Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

公开(公告)号：US20220368287A1

公开(公告)日：2022-11-17

申请号：US17843372

申请日：2022-06-17

Applicant: pSemi Corporation

Inventor： Jonathan James Klaren ,  David Kovac ,  Eric S. Shapiro ,  Christopher C. Murphy ,  Robert Mark Englekirk ,  Keith Bargroff ,  Tero Tapio Ranta

IPC: H03F1/22 ,  H03F3/195 ,  H03F3/213 ,  H03F3/24 ,  H03F1/30 ,  H03F1/56 ,  H03F3/193

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

公开(公告)号：US10971359B2

公开(公告)日：2021-04-06

申请号：US16689836

申请日：2019-11-20

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

公开(公告)号：US20210026391A1

公开(公告)日：2021-01-28

申请号：US16989435

申请日：2020-08-10

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

IPC: G05F3/26 ,  H03M1/66 ,  G05F3/24

Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

公开(公告)号：US20200350267A1

公开(公告)日：2020-11-05

申请号：US16875615

申请日：2020-05-15

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L23/60 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  H01L23/552 ,  H01L29/10 ,  H01L23/66 ,  H03K17/0412 ,  H01L21/762 ,  H03K17/0416 ,  H03K17/042 ,  H03K17/14

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.