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公开(公告)号：US5124580A
公开(公告)日：1992-06-23
申请号：US693815
申请日：1991-04-30
Applicant: James A. Matthews , Geert Rosseel
Inventor： James A. Matthews , Geert Rosseel
IPC: H03K17/567 , H03K19/08 , H03K19/086 , H03K19/0944
CPC classification number: H03K19/09448
Abstract: A BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a p-channel metal-oxide-semiconductor (PMOS) transistor. An emitter follower, having its base coupled to the collector of one of the bipolar transistors and its collector connected to the first power supply potential, provides the output signal. NMOS transistors are used as current sources for biasing the emitter-coupled pair and the emitter follower. A circuit means provides a feedback signal coupled to the gates of the PMOS transistors for dynamically controlling the load resistance presented to said emitter coupled pair.
Abstract translation: BiCMOS逻辑电路利用发射极耦合的双极晶体管对将输入信号与逻辑参考电平进行差分比较。 每个双极晶体管由p沟道金属氧化物半导体（PMOS）晶体管电阻负载。 射极跟随器，其基极耦合到双极晶体管之一的集电极，并且其集电极连接到第一电源电位，提供输出信号。 NMOS晶体管用作用于偏置发射极耦合对和射极跟随器的电流源。 电路装置提供耦合到PMOS晶体管的栅极的反馈信号，用于动态地控制呈现给所述发射极耦合对的负载电阻。
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公开(公告)号：US1689292A
公开(公告)日：1928-10-30
申请号：US64749423
申请日：1923-06-25
Applicant: WESTERN ELECTRIC CO
Inventor： O'NEILL HENRY W
CPC classification number: G01S1/02
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公开(公告)号：US10204055B2
公开(公告)日：2019-02-12
申请号：US15698180
申请日：2017-09-07
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F12/08 , G06F9/30 , G06F12/0875 , G06F9/34 , G06F9/38
Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
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24.发明授权Processor and method for executing instructions requiring wide operands for multiply matrix operations 有权用于执行需要用于多重矩阵运算的广泛操作数的指令的处理器和方法公开(公告)号：US07952587B2
公开(公告)日：2011-05-31
申请号：US11982230
申请日：2007-10-31
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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25.发明申请公开(公告)号：US20090113187A1
公开(公告)日：2009-04-30
申请号：US11982106
申请日：2007-10-31
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/315
CPC classification number: G06F9/30014 , G06F9/30007 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/34 , G06F9/3824 , G06F9/383 , G06F9/3885 , G06F12/0886
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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Patent Agency Ranking
公开(公告)号：US07516308B2
公开(公告)日：2009-04-07
申请号：US10436340
申请日：2003-05-13
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
IPC: G06F9/302
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A system and method expands a source operand to a width greater than that of a general purpose register or a data path. Operands are provided substantially larger than the data path width of a processor. The general purpose register specifies a memory address from which several data path widths of data are read. A data path functional unit is augmented with dedicated storage to which the memory operand is copied on initial execution of the instruction. Further instructions specifying the same memory address read the dedicated storage to obtain the operand value, upon verification that the memory operand has not been altered by intervening instructions. If the memory operand remains current, the memory operand fetch is combined with register operands in the functional unit, producing a result the size of a general register, so no dedicated storage is required for the result.
Abstract translation: 系统和方法将源操作数扩展到大于通用寄存器或数据路径的宽度。 提供的操作数比处理器的数据路径宽度大得多。 通用寄存器指定读取数据的数据路径宽度的存储器地址。 在指令的初始执行时，对存储器操作数进行复制的专用存储器来增强数据路径功能单元。 指定相同存储器地址的进一步指令读取专用存储器以获得操作数值，在验证存储器操作数没有被介入指令改变时。 如果存储器操作数保持当前，则存储器操作数获取与功能单元中的寄存器操作数组合，产生通用寄存器的大小的结果，因此不需要专用存储器。
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27.发明申请Processor for executing switch and translate instructions requiring wide operands 有权用于执行切换和转换需要广泛操作数的指令的处理器公开(公告)号：US20080189512A1
公开(公告)日：2008-08-07
申请号：US11982171
申请日：2007-10-31
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/00
CPC classification number: G06F12/02 , G06F9/30007 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/383 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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公开(公告)号：US07353367B2
公开(公告)日：2008-04-01
申请号：US10712430
申请日：2003-11-14
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
IPC: G06F9/315
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.
Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可操作以解码和执行指定移位量的单个指令和包含多个数据元素的寄存器，其中所述执行单元可操作以移位每个 多个数据元素的移位量产生第二多个数据元素; 并且提供第二多个数据元素作为连接结果。
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公开(公告)号：US07301541B2
公开(公告)日：2007-11-27
申请号：US10616303
申请日：2003-07-10
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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公开(公告)号：US07260708B2
公开(公告)日：2007-08-21
申请号：US10705946
申请日：2003-11-13
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
IPC: G06F9/315
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.
Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可操作以解码和执行指定移位量的单个指令和包含多个数据元素的寄存器，其中所述执行单元可操作以移位每个 多个数据元素的移位量产生第二多个数据元素; 并且提供第二多个数据元素作为连接结果。
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