Abstract:
A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.
Abstract:
A Digitial Radio Mondiale (DRM) receiver and demodulation method includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. This reduces the processing/computational requirements and the design complexity of the DRM receiver.
Abstract:
A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core.
Abstract:
An audio amplifier device includes a power supply having an output for providing a supply voltage, a voltage divider connected to the output of the power supply for providing a divided supply voltage, and an audio amplifier that further includes a supply voltage rejection circuit. The audio amplifier has a first input for receiving an input audio signal, a second input for receiving the supply voltage, a third input for receiving a supply voltage rejection signal for the supply voltage rejection circuit, and an output for providing an output audio signal. A power-off noise suppression circuit has a first input for receiving the divided supply voltage and an output for providing the supply voltage rejection signal. The power-off noise suppression circuit sets the supply voltage rejection signal equal to the divided supply voltage during power-off of the power supply so that a rate of decrease of the supply voltage is greater than a rate of decrease of the supply voltage rejection signal for reducing noise in the output audio signal during the power-off.
Abstract:
Embodiments of the present disclosure relate to an interconnect package, a method of forming the interconnect package, and a power module. The interconnect package includes a first insulating layer, a source connecting portion disposed on a surface of the first insulating layer and adapted to electrically connect a source pad to a substrate, a second insulating layer, and a gate connecting portion disposed between the first insulating layer and the second insulating layer and adapted to electrically connect a gate pad to the substrate. In addition, the second insulating layer has a plurality of gate openings and a plurality of source openings running therethrough and wherein a first surface of the second insulating layer is configured to attach to a surface of the first insulating layer such that a plurality of portions of the source connecting portion are exposed from the plurality of source openings on a second surface of the second insulating layer opposite the first surface, and such that a plurality of portions of the gate connecting portion are exposed from the plurality of gate openings on the second surface of the second insulating layer.
Abstract:
A differential amplifier receives a differential input signal and generates an output signal at an output node. An auxiliary circuit coupled to the differential amplifier operates to improve slew rate response. In quiescent and small signal situations with respect to the differential input signal, the auxiliary circuit does not alter or change operation of the differential amplifier. However, in situations where a large signal change is experienced with respect to the differential input signal, the auxiliary circuit functions to speed up the sourcing and sinking current to/from the output node. A stability compensation capacitor coupled to the output node is accordingly more quickly charged or discharged and an improvement in slew rate performance of the differential amplifier is experienced.
Abstract:
A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.
Abstract:
A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.
Abstract:
A compensated regulator includes a transconductance stage having a positive input for receiving a reference voltage, a negative input, and an output, an adjustable compensation block coupled between the output of the transconductance stage and ground, a feedback circuit having a first node coupled to the output of the compensated regulator, a second node coupled to the negative input of the transconductance stage, and a third node coupled to ground, and a driver stage having an input coupled to the output of the transconductance stage, a current output coupled to the output of the compensated regulator, and a sense output coupled to the adjustable compensation block.
Abstract:
A voltage regulator includes a power transistor receiving a drive current, and a current limit protection circuit connected to the power transistor. The current limit protection circuit includes a first resistance connected to the power transistor for sensing an output current, a limit switch transistor connected to the power transistor and to the first resistance, and a current generator and second resistance connected thereto. The current generator and second resistance biases the limit switch transistor to divert drive current from the power transistor based upon the output current through the first resistance exceeding a threshold. The first resistance has a value less than a value of the second resistance. The first resistance can be made considerably smaller than otherwise to thereby reduce power consumption. The temperature coefficient for the second resistance is balanced with respect to a temperature coefficient for the first resistance so that a output current from the voltage regulator is not sensitive to temperature variations.