DRIVER WITH CONTROL INTERFACE FACILITATING USE OF THE DRIVER WITH VARIED DC-TO-DC CONVERTER CIRCUITS
    21.
    发明申请
    DRIVER WITH CONTROL INTERFACE FACILITATING USE OF THE DRIVER WITH VARIED DC-TO-DC CONVERTER CIRCUITS 有权
    具有控制接口的驱动器可以使用变频器直流到直流转换器电路

    公开(公告)号:US20090039857A1

    公开(公告)日:2009-02-12

    申请号:US12254718

    申请日:2008-10-20

    CPC classification number: H02M3/156 H02M3/33507

    Abstract: A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.

    Abstract translation: 用于DC-DC转换器的驱动器,其可以利用反激式或降压 - 升压转换器电路。 驱动器包括驱动电路和接口电路。 接口电路具有感测来自直流电源的输入电压并且向驱动器选择器产生传感器信号的传感器。 驱动器选择器将传感器信号与比较电压进行比较以确定转换器电路的类型,然后将选择器信号发送到用于控制驱动器电路的一个或多个部件的驱动器电路,例如逻辑电路 用于驱动转换器来调节转换器输出。 传感器包括检测电阻器以及电流检测放大器,其适于连接到电源的高侧或低侧,同时仍然产生基本相等的输出电压或传感器信号。

    DRM receiver and demodulation method
    22.
    发明申请
    DRM receiver and demodulation method 有权
    DRM接收机和解调方法

    公开(公告)号:US20080292027A1

    公开(公告)日:2008-11-27

    申请号:US12079953

    申请日:2008-03-28

    CPC classification number: H04L27/265 H04B1/0003

    Abstract: A Digitial Radio Mondiale (DRM) receiver and demodulation method includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. This reduces the processing/computational requirements and the design complexity of the DRM receiver.

    Abstract translation: 数字无线电广播(DRM)接收机和解调方法包括可编程下行采样器和可编程N点快速傅里叶变换(FFT),以便在接收的DRM编码RF信号中恢复和解调OFDM符号。 所接收的信号以可操作地整数下采样的速率进行数字采样,以在OFDM符号的有用部分中实现N个采样,以输入到N点FFT,其中N等于2的幂。 FFT的下采样率和大小(N点)取决于DRM编码和传输参数,特别是鲁棒性模式和频谱占用。 这降低了DRM接收机的处理/计算要求和设计复杂度。

    OPAMP-LESS BANDGAP VOLTAGE REFERENCE WITH HIGH PSRR AND LOW VOLTAGE IN CMOS PROCESS
    23.
    发明申请
    OPAMP-LESS BANDGAP VOLTAGE REFERENCE WITH HIGH PSRR AND LOW VOLTAGE IN CMOS PROCESS 有权
    CMOS工艺中具有高PSRR和低电压的无漏带电压参考

    公开(公告)号:US20080224761A1

    公开(公告)日:2008-09-18

    申请号:US12049127

    申请日:2008-03-14

    CPC classification number: G05F3/30

    Abstract: A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core.

    Abstract translation: 电路包括连接在调节电压和接地参考之间的无OPAMP的带隙电压产生核心电路,以产生输出带隙电压。 预调节器电路从未调节的电源电压产生调节电压。 预调节器电路包括可操作以稳定调节电压的负反馈回路和可操作以为调节电压源电流的电流源,该电流源镜像无OPAMP的带隙电压产生核心电路的PTAT电流。 核心电路还包括负反馈回路和正反馈回路,负和正反馈回路用于均衡内核内的两个内部电压。

    Power-off noise suppression circuit and associated methods for an audio amplifier device
    24.
    发明授权
    Power-off noise suppression circuit and associated methods for an audio amplifier device 有权
    断电噪声抑制电路及音频放大器装置的相关方法

    公开(公告)号:US06954537B2

    公开(公告)日:2005-10-11

    申请号:US10038848

    申请日:2001-12-31

    CPC classification number: H03F1/305 H03G3/348

    Abstract: An audio amplifier device includes a power supply having an output for providing a supply voltage, a voltage divider connected to the output of the power supply for providing a divided supply voltage, and an audio amplifier that further includes a supply voltage rejection circuit. The audio amplifier has a first input for receiving an input audio signal, a second input for receiving the supply voltage, a third input for receiving a supply voltage rejection signal for the supply voltage rejection circuit, and an output for providing an output audio signal. A power-off noise suppression circuit has a first input for receiving the divided supply voltage and an output for providing the supply voltage rejection signal. The power-off noise suppression circuit sets the supply voltage rejection signal equal to the divided supply voltage during power-off of the power supply so that a rate of decrease of the supply voltage is greater than a rate of decrease of the supply voltage rejection signal for reducing noise in the output audio signal during the power-off.

    Abstract translation: 音频放大器装置包括具有用于提供电源电压的输出的电源,连接到电源的输出的分压器,用于提供分开的电源电压,以及还包括电源电压抑制电路的音频放大器。 音频放大器具有用于接收输入音频信号的第一输入端,用于接收电源电压的第二输入端,用于接收电源电压抑制电路的电源电压抑制信号的第三输入端和用于提供输出音频信号的输出端。 断电噪声抑制电路具有用于接收划分的电源电压的第一输入端和用于提供电源电压抑制信号的输出端。 断电噪声抑制电路将电源电压抑制信号设置为等于电源断电期间的分压电源电压,使得电源电压的降低率大于电源电压抑制信号的减小率 用于在断电期间降低输出音频信号中的噪声。

    INTERCONNECT PACKAGE, METHOD OF FORMING THE SAME AND POWER MODULE

    公开(公告)号:US20250006633A1

    公开(公告)日:2025-01-02

    申请号:US18754005

    申请日:2024-06-25

    Abstract: Embodiments of the present disclosure relate to an interconnect package, a method of forming the interconnect package, and a power module. The interconnect package includes a first insulating layer, a source connecting portion disposed on a surface of the first insulating layer and adapted to electrically connect a source pad to a substrate, a second insulating layer, and a gate connecting portion disposed between the first insulating layer and the second insulating layer and adapted to electrically connect a gate pad to the substrate. In addition, the second insulating layer has a plurality of gate openings and a plurality of source openings running therethrough and wherein a first surface of the second insulating layer is configured to attach to a surface of the first insulating layer such that a plurality of portions of the source connecting portion are exposed from the plurality of source openings on a second surface of the second insulating layer opposite the first surface, and such that a plurality of portions of the gate connecting portion are exposed from the plurality of gate openings on the second surface of the second insulating layer.

    Differential amplifier having an improved slew rate
    26.
    发明授权
    Differential amplifier having an improved slew rate 有权
    差分放大器具有改善的转换速率

    公开(公告)号:US07548117B2

    公开(公告)日:2009-06-16

    申请号:US11654976

    申请日:2007-01-18

    Abstract: A differential amplifier receives a differential input signal and generates an output signal at an output node. An auxiliary circuit coupled to the differential amplifier operates to improve slew rate response. In quiescent and small signal situations with respect to the differential input signal, the auxiliary circuit does not alter or change operation of the differential amplifier. However, in situations where a large signal change is experienced with respect to the differential input signal, the auxiliary circuit functions to speed up the sourcing and sinking current to/from the output node. A stability compensation capacitor coupled to the output node is accordingly more quickly charged or discharged and an improvement in slew rate performance of the differential amplifier is experienced.

    Abstract translation: 差分放大器接收差分输入信号并在输出节点处产生输出信号。 耦合到差分放大器的辅助电路用于提高转换速率响应。 在相对于差分输入信号的静止和小信号情况下,辅助电路不会改变或改变差分放大器的工作。 然而,在相对于差分输入信号经历大的信号变化的情况下,辅助电路用于加速来自/来自输出节点的电流和吸收电流。 耦合到输出节点的稳定性补偿电容器相应地更快速地充电或放电,并且经历差分放大器的压摆率性能的改善。

    Zero-waiting-current precise over-voltage comparator
    27.
    发明授权
    Zero-waiting-current precise over-voltage comparator 有权
    零等待电流精确过电压比较器

    公开(公告)号:US07525350B2

    公开(公告)日:2009-04-28

    申请号:US11831769

    申请日:2007-07-31

    CPC classification number: G01R19/16519 G01R19/16576

    Abstract: A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.

    Abstract translation: 精确的过电压比较器在正常工作条件下具有零等待电流特性。 NMOS晶体管与其他电路元件结合使用以调节过电压比较器。 对于正常的电源电压,比较器保持待机状态,不消耗静态电流。

    ZERO-WAITING-CURRENT PRECISE OVER-VOLTAGE COMPARATOR
    28.
    发明申请
    ZERO-WAITING-CURRENT PRECISE OVER-VOLTAGE COMPARATOR 有权
    零等级电流精度过压比较器

    公开(公告)号:US20080061844A1

    公开(公告)日:2008-03-13

    申请号:US11831769

    申请日:2007-07-31

    CPC classification number: G01R19/16519 G01R19/16576

    Abstract: A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.

    Abstract translation: 精确的过电压比较器在正常工作条件下具有零等待电流特性。 NMOS晶体管与其他电路元件结合使用以调节过电压比较器。 对于正常的电源电压,比较器保持待机状态,不消耗静态电流。

    LOW DROP-OUT LINEAR REGULATOR INCLUDING A STABLE COMPENSATION METHOD AND CIRCUIT FOR PARTICULAR USE IN AUTOMOTIVE APPLICATIONS
    29.
    发明申请
    LOW DROP-OUT LINEAR REGULATOR INCLUDING A STABLE COMPENSATION METHOD AND CIRCUIT FOR PARTICULAR USE IN AUTOMOTIVE APPLICATIONS 有权
    低压降线性稳压器,包括稳定的补偿方法和电路,用于汽车应用中的特殊应用

    公开(公告)号:US20070216382A1

    公开(公告)日:2007-09-20

    申请号:US11684434

    申请日:2007-03-09

    Inventor: DaSong Lin Gang Zha

    CPC classification number: G05F1/575

    Abstract: A compensated regulator includes a transconductance stage having a positive input for receiving a reference voltage, a negative input, and an output, an adjustable compensation block coupled between the output of the transconductance stage and ground, a feedback circuit having a first node coupled to the output of the compensated regulator, a second node coupled to the negative input of the transconductance stage, and a third node coupled to ground, and a driver stage having an input coupled to the output of the transconductance stage, a current output coupled to the output of the compensated regulator, and a sense output coupled to the adjustable compensation block.

    Abstract translation: 补偿稳压器包括跨导级,其具有用于接收参考电压的正输入端,负输入端和输出端,耦合在跨导级与地的输出之间的可调补偿块,具有耦合到 补偿调节器的输出,耦合到跨导级的负输入的第二节点和耦合到地的第三节点,以及具有耦合到跨导级的输出的输入的驱动级,耦合到输出的电流输出 并且耦合到可调补偿块的感测输出。

    CURRENT LIMIT PROTECTION CIRCUIT FOR A VOLTAGE REGULATOR
    30.
    发明申请
    CURRENT LIMIT PROTECTION CIRCUIT FOR A VOLTAGE REGULATOR 有权
    电流稳压器的电流限制保护电路

    公开(公告)号:US20020118002A1

    公开(公告)日:2002-08-29

    申请号:US10039043

    申请日:2001-12-31

    Inventor: Wen Li Luo

    CPC classification number: G05F1/575 G05F1/565

    Abstract: A voltage regulator includes a power transistor receiving a drive current, and a current limit protection circuit connected to the power transistor. The current limit protection circuit includes a first resistance connected to the power transistor for sensing an output current, a limit switch transistor connected to the power transistor and to the first resistance, and a current generator and second resistance connected thereto. The current generator and second resistance biases the limit switch transistor to divert drive current from the power transistor based upon the output current through the first resistance exceeding a threshold. The first resistance has a value less than a value of the second resistance. The first resistance can be made considerably smaller than otherwise to thereby reduce power consumption. The temperature coefficient for the second resistance is balanced with respect to a temperature coefficient for the first resistance so that a output current from the voltage regulator is not sensitive to temperature variations.

    Abstract translation: 电压调节器包括接收驱动电流的功率晶体管和连接到功率晶体管的限流保护电路。 电流限制保护电路包括连接到用于感测输出电流的功率晶体管的第一电阻,连接到功率晶体管和第一电阻的限位开关晶体管,以及与其连接的电流发生器和第二电阻。 电流发生器和第二电阻偏置限位开关晶体管,以基于超过阈值的第一电阻的输出电流从功率晶体管转移驱动电流。 第一电阻具有小于第二电阻值的值。 第一个电阻可以比其他电阻小得多,从而降低功耗。 第二电阻的温度系数相对于第一电阻的温度系数平衡,使得来自电压调节器的输出电流对温度变化不敏感。

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