公开(公告)号：US09246539B2

公开(公告)日：2016-01-26

申请号：US14637207

申请日：2015-03-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Daichi Imamura ,  Takashi Iwai ,  Kazunori Inogai ,  Sadaki Futagi ,  Atsushi Matsumoto

IPC: H04W4/00 ,  H04W72/04 ,  H04B1/707 ,  H04J13/00 ,  H04J13/22 ,  H04L23/02 ,  H04W74/08 ,  H04J13/10 ,  H04L27/26

CPC classification number: H04W74/0833 ,  H04B1/707 ,  H04B1/7083 ,  H04B2201/70702 ,  H04B2201/70713 ,  H04J13/0062 ,  H04J13/102 ,  H04J13/22 ,  H04L5/0048 ,  H04L23/02 ,  H04L27/2613 ,  H04W72/04 ,  H04W72/0446 ,  H04W72/0453 ,  H04W74/0875

Abstract: A sequence allocating method and apparatus wherein in a system where a plurality of different Zadoff-Chu sequences or GCL sequences are allocated to a single cell, the arithmetic amount and circuit scale of a correlating circuit at a receiving end can be reduced. In ST201, a counter (a) and a number (p) of current sequence allocations are initialized, and in ST202, it is determined whether the number (p) of current sequence allocations is coincident with a number (K) of allocations to one cell. In ST203, it is determined whether the number (K) of allocations to the one cell is odd or even. If K is even, in ST204-ST206, sequence numbers (r=a and r=N−a), which are not currently allocated, are combined and then allocated. If K is odd, in ST207-ST212, for sequences that cannot be paired, one of sequence numbers (r=a and r=N−a), which are not currently allocated, is allocated.

Abstract translation: 一种序列分配方法和装置，其中在将多个不同的Zadoff-Chu序列或GCL序列分配给单个小区的系统中，可以减少接收端的相关电路的算术量和电路规模。 在ST201中，初始化当前序列分配的计数器（a）和数量（p），并且在ST202中，确定当前序列分配的数量（p）是否与一个分配的数量（K）一致 细胞。 在ST203中，确定对一个单元的分配的数量（K）是奇数还是偶数。 如果K是偶数，则在ST204-ST206中，组合然后分配未被分配的序列号（r = a和r = N-a）。 如果K是奇数，则在ST207-ST212中，对于不能配对的序列，分配未分配的序列号（r = a和r = N-a）中的一个。

公开(公告)号：US20150372713A1

公开(公告)日：2015-12-24

申请号：US14725363

申请日：2015-05-29

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Vincent LENOIR ,  Didier LATTARD ,  Warody LOMBARDI

IPC: H04B1/709 ,  H04L27/22 ,  H04L27/26

CPC classification number: H04B1/709 ,  H04B1/70752 ,  H04B2201/70713 ,  H04L27/22 ,  H04L27/2601

Abstract: A method for decoding a data symbol carried by a signal received by a receiver of a communication system, the data symbol being modulated by a spread code sequence selected from a plurality of spread code sequences being quasi-orthogonal to each other to differentiate the symbol from other data symbols, and being received as a set of modulation bits, the method including a step of correlating the modulated data symbol received with each of the plurality of spread code sequences, and the correlating step is preceded by a step of sub-sampling the modulated data symbol received to mask one or more of the modulation bits therein, such that the step of correlating the sub-sampled data symbol received is carried out only for the non-masked modulation bits. It extends to a demodulation unit configured for the implementation of this method, and to a receiver integrating such a unit.

Abstract translation: 一种用于对由通信系统的接收机接收的信号承载的数据符号进行解码的方法，所述数据符号由从彼此准正交的多个扩展码序列中选择的扩展码序列调制，以将符号与 其他数据符号，并且作为一组调制比特被接收，该方法包括使接收的调制数据符号与多个扩展码序列中的每一个进行相关的步骤和相关步骤，之后是对 接收的调制数据符号以掩蔽其中的一个或多个调制位，使得仅对于未被掩蔽的调制位执行将接收的子采样数据符号相关的步骤。 它扩展到被配置用于实现该方法的解调单元，以及集成这样的单元的接收器。

公开(公告)号：US09025545B2

公开(公告)日：2015-05-05

申请号：US13614451

申请日：2012-09-13

Applicant: Daichi Imamura ,  Takashi Iwai ,  Kazunori Inogai ,  Sadaki Futagi ,  Atsushi Matsumoto

Inventor： Daichi Imamura ,  Takashi Iwai ,  Kazunori Inogai ,  Sadaki Futagi ,  Atsushi Matsumoto

IPC: H04W4/00 ,  H04W72/04 ,  H04J13/00 ,  H04J13/22 ,  H04J13/10 ,  H04L27/26

CPC classification number: H04W74/0833 ,  H04B1/707 ,  H04B1/7083 ,  H04B2201/70702 ,  H04B2201/70713 ,  H04J13/0062 ,  H04J13/102 ,  H04J13/22 ,  H04L5/0048 ,  H04L23/02 ,  H04L27/2613 ,  H04W72/04 ,  H04W72/0446 ,  H04W72/0453 ,  H04W74/0875

Abstract: A sequence allocating method and apparatus wherein in a system where a plurality of different Zadoff-Chu sequences or GCL sequences are allocated to a single cell, the arithmetic amount and circuit scale of a correlating circuit at a receiving end can be reduced. In ST201, a counter (a) and a number (p) of current sequence allocations are initialized, and in ST202, it is determined whether the number (p) of current sequence allocations is coincident with a number (K) of allocations to one cell. In ST203, it is determined whether the number (K) of allocations to the one cell is odd or even. If K is even, in ST204-ST206, sequence numbers (r=a and r=N−a), which are not currently allocated, are combined and then allocated. If K is odd, in ST207-ST212, for sequences that cannot be paired, one of sequence numbers (r=a and r=N−a), which are not currently allocated, is allocated.

Abstract translation: 一种序列分配方法和装置，其中在将多个不同的Zadoff-Chu序列或GCL序列分配给单个小区的系统中，可以减少接收端的相关电路的算术量和电路规模。 在ST201中，初始化当前序列分配的计数器（a）和数量（p），并且在ST202中，确定当前序列分配的数量（p）是否与一个分配的数量（K）一致 细胞。 在ST203中，确定对一个单元的分配的数量（K）是奇数还是偶数。 如果K是偶数，则在ST204-ST206中，组合然后分配未被分配的序列号（r = a和r = N-a）。 如果K是奇数，则在ST207-ST212中，对于不能配对的序列，分配未分配的序列号（r = a和r = N-a）中的一个。

公开(公告)号：US08386549B1

公开(公告)日：2013-02-26

申请号：US12042260

申请日：2008-03-04

Applicant: Alvin M. Despain

Inventor： Alvin M. Despain

IPC: G06F17/10

CPC classification number: G06F17/10 ,  H03H17/0248 ,  H04B1/7105 ,  H04B2201/70713 ,  H04B2201/709745 ,  H04B2201/709763 ,  H04B2201/709772

Abstract: Multistage Wiener filters (MWF) represent a component of the MWF as an un-normalized vector of filter coefficients within a finite impulse response (FIR) filter in a manner that avoids reliance on the 2-norm operation of the un-normalized vector of coefficients. The 2-norm operation can be replaced by less expensive operations performed elsewhere in the MWF. Preferably the filter adds only a few additional addition, subtraction and multiplication operations to compensate for the elimination of the square root and the division operations used for the 2-norm operation. As a result, it is possible to eliminate all or nearly all of the square rod and arithmetic division operations of at least some implementations of the MWF.

Abstract translation: 多级维纳滤波器（MWF）以有限脉冲响应（FIR）滤波器中的滤波器系数的非归一化向量作为MWF的分量，以避免依赖于系数的非归一化矢量的2范数运算 。 可以通过在MWF其他地方执行的较廉价的操作来代替2规范操作。 优选地，滤波器仅添加少量附加，减法和乘法运算，以补偿平方根的消除和用于2范数运算的除法运算。 结果，可以消除MWF的至少一些实施方式的所有或几乎所有的方棒和算术分割操作。