公开(公告)号：US11336280B2

公开(公告)日：2022-05-17

申请号：US17150156

申请日：2021-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe Maiocchi ,  Ezio Galbiati ,  Michele Boscolo Berto ,  Maurizio Ricci

IPC: H03K17/687 ,  H02M3/157 ,  H02M1/00

Abstract: A half-bridge control circuit comprises an input terminal, an output terminal for providing a pulsed signal to a half-bridge driver circuit configured to drive two electronic switches connected between two supply terminals, and a feedback terminal for receiving a feedback signal indicative of the instantaneous voltage value at a switching node between the two electronic switches. A selector circuit provides a digital feedback signal. A subtractor generates an error signal by subtracting the digital feedback signal from the reference signal. An integrator generates an integration signal by integrating the value of the error signal. A down-scale circuit generates a reduced resolution integration signal by discarding one or more least significant bits of the integration signal. A sampling circuit generates a sampled integration signal by sampling the reduced resolution integration signal. A pulse generator circuit generates the pulsed signal as a function of the sampled integration signal.

公开(公告)号：US20220149844A1

公开(公告)日：2022-05-12

申请号：US17450711

申请日：2021-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Liliana Arcidiacono ,  Alessandro Nicolosi ,  Valeria Bottarel

IPC: H03K19/17736 ,  H03K19/08

Abstract: A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

公开(公告)号：US20220145873A1

公开(公告)日：2022-05-12

申请号：US17519294

申请日：2021-11-04

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Michele Alessio DELLUTRI ,  Fabio PASSANITI ,  Enrico Rosario ALESSI

IPC: F04B43/12 ,  F04B49/06

Abstract: Various embodiments provide a device for measuring the flow of fluid inside a tube moved by a peristaltic pump is provided with: a detection electrode arrangement coupled to the tube to detect an electrostatic charge variation originated by the mechanical action of the peristaltic pump on the tube; a signal processing stage, electrically coupled to the detection electrode arrangement to generate an electrical charge variation signal; and a processing unit, coupled to the signal processing stage to receive and process in the frequency domain the electrical charge variation signal to obtain information on the flow of a fluid that flows through the tube based on the analysis of frequency characteristics of the electrical charge variation signal.

公开(公告)号：US11329568B2

公开(公告)日：2022-05-10

申请号：US16933534

申请日：2020-07-20

Applicant: STMicroelectronics S.r.l.

Inventor： Claudio Adragna ,  Giuseppe Gattavari ,  Paolo Mattavelli ,  Enrico Orietti ,  Giorgio Spiazzi

IPC: H02M3/335

Abstract: A PWM controlled multi-phase resonant voltage converter may include a plurality of primary windings powered through respective half-bridges, and as many secondary windings connected to an output terminal of the converter and magnetically coupled to the respective primary windings. The primary or secondary windings may be connected such that a real or virtual neutral point is floating.

公开(公告)号：US11329131B2

公开(公告)日：2022-05-10

申请号：US17096635

申请日：2020-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti ,  Alfio Guarnera

IPC: H01L29/08 ,  H01L29/16

Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.

公开(公告)号：US11328768B2

公开(公告)日：2022-05-10

申请号：US17119979

申请日：2020-12-11

Applicant: STMicroelectronics S.r.l.

Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Davide Manfré ,  Cesare Torti

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/02 ,  G11C7/06

Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

公开(公告)号：US11327772B2

公开(公告)日：2022-05-10

申请号：US16422469

申请日：2019-05-24

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Silvio Fiorese

IPC: G06F9/4401 ,  G06F8/65 ,  G06F9/445

Abstract: A method for method of setting up a processing system includes determining availability of user-provided platform information indicative of a first memory platform out of a plurality of memory platforms. In response to determining that the user-provided platform information is available at the first memory platform, a boot loader code is read from the first memory platform. In response to determining that the user-provided platform information is not available, test availability of the boot loader code in another memory platform of the plurality of memory platforms, and read the boot loader code from the another memory platform upon testing the availability of the boot loader code in the another memory platform.

公开(公告)号：US20220137128A1

公开(公告)日：2022-05-05

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar GOYAL ,  Deepak BARANWAL ,  Thomas SZURMANT ,  Nicolas Bernard GROSSIER

IPC: G01R31/317 ,  G01R31/3185

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

公开(公告)号：US11317219B2

公开(公告)日：2022-04-26

申请号：US16693003

申请日：2019-11-22

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Matteo Perletti ,  Federico Vercesi ,  Silvia Adorno ,  Giorgio Allegato

IPC: H04R19/00 ,  H04R19/04 ,  B81B7/00 ,  B81C1/00 ,  H04R31/00 ,  H04R1/08 ,  H04R1/28

Abstract: A method for manufacturing a filtering module comprising the steps of: forming a multilayer body comprising a filter layer of semiconductor material and having a thickness of less than 10 μm, a first structural layer coupled to a first side of the filter layer, and a second structural layer coupled to a second side, opposite to the first side, of the filter layer; forming a recess in the first structural layer, which extends throughout its thickness; removing selective portions, exposed through the recess, of the filter layer to form a plurality of openings, which extend throughout the thickness of the filter layer; and completely removing the second structural layer to connect fluidically the first and second sides of the filter layer, thus forming a filtering membrane designed to inhibit passage of contaminating particles.

公开(公告)号：US20220118480A1

公开(公告)日：2022-04-21

申请号：US17497542

申请日：2021-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Domenico GIUSTI ,  Fabio QUAGLIA ,  Marco FERRERA

IPC: B06B1/06 ,  B81B7/00 ,  H01L41/09 ,  H01L41/113 ,  B81B3/00 ,  B81C1/00

Abstract: A PMUT device includes a membrane element extending perpendicularly to a first direction and configured to generate and receive ultrasonic waves by oscillating about an equilibrium position. At least two piezoelectric elements are included, with each one located over the membrane element along the first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. The membrane element has a lobed shape along a plane perpendicular to the first direction, with the lobed shape including at least two lobes. The membrane element includes for each piezoelectric member a corresponding membrane portion including a corresponding lobe, with each piezoelectric member being located over its corresponding membrane portion.