公开(公告)号：US09049061B2

公开(公告)日：2015-06-02

申请号：US13640733

申请日：2012-04-11

Applicant: Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

Inventor： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

IPC: H01L27/092 ,  H01L21/265 ,  H04L21/02

CPC classification number: H04L21/02 ,  H01L21/265 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.

Abstract translation: 本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。 本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层， 蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。

公开(公告)号：US09024435B2

公开(公告)日：2015-05-05

申请号：US13379347

申请日：2011-08-12

Applicant: Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

IPC: H01L23/34 ,  H01L23/522 ,  H01L23/467 ,  H01L23/473

CPC classification number: H01L23/522 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.

Abstract translation: 提供半导体器件，其形成方法和封装结构。 半导体器件包括：形成金属氧化物半导体场效应晶体管（MOSFET）的半导体衬底; 介电层，设置在所述半导体衬底上并覆盖所述MOSFET，其中在所述电介质层中形成多个互连结构; 以及嵌入在互连结构之间的电介质层中的至少一个散热路径，用于使液体或气体在散热路径中循环，其中散热路径的开口暴露在介电层的表面上。 本发明可以提高散热效率，防止芯片过热。

公开(公告)号：US08987127B2

公开(公告)日：2015-03-24

申请号：US14361944

申请日：2012-03-23

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

公开(公告)号：US08606836B2

公开(公告)日：2013-12-10

申请号：US12868200

申请日：2010-08-25

Applicant: Ting-Hsuan Chen ,  Gaung-Hui Gu ,  Ying-Chiang Hu ,  Tsung-Min Hsieh ,  Jun-Chao Zhao

Inventor： Ting-Hsuan Chen ,  Gaung-Hui Gu ,  Ying-Chiang Hu ,  Tsung-Min Hsieh ,  Jun-Chao Zhao

IPC: G06F17/10

CPC classification number: G06F17/14 ,  H04J1/05

Abstract: An apparatus and method for frequency division and filtering are provided. The apparatus includes a memory unit, an extrema calculation unit, and an envelope calculation unit. The memory unit is for storing sample data. The extrema calculation unit is for outputting and storing a number of maximum values and a number of minimum values to the memory unit according to the sample data. The envelope calculation unit is for calculating a mean envelope according to the maximum values and the minimum values, wherein within a duration when the envelope calculation unit respectively calculates an upper envelope and a lower envelope according to the maximum values and the minimum values, the envelope calculation unit outputs a value of the mean envelope to the memory unit according to a value of the upper envelope and a value of the lower envelope with respect to a corresponding identical address.

Abstract translation: 提供了一种用于分频和滤波的装置和方法。 该装置包括存储器单元，极值计算单元和包络计算单元。 存储单元用于存储采样数据。 极值计算单元用于根据样本数据将多个最大值和最小值的数量存储到存储器单元。 信封计算单元用于根据最大值和最小值计算平均包络，其中在包络计算单元根据最大值和最小值分别计算上包络和下包络的持续时间内，包络 计算单元根据上包络的值和相对于相应相同地址的下包络的值将平均包络的值输出到存储器单元。

公开(公告)号：US20130302952A1

公开(公告)日：2013-11-14

申请号：US13580963

申请日：2012-06-07

Applicant: Jun Luo ,  Jian Deng ,  Chao Zhao ,  Junfeng Li ,  Dapeng Chen

Inventor： Jun Luo ,  Jian Deng ,  Chao Zhao ,  Junfeng Li ,  Dapeng Chen

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a gate stack structure on a substrate; forming source and drain regions as well as a gate spacer on both sides of the gate stack structure; depositing a first metal layer on the source and drain regions; performing a first annealing such that the first metal layer reacts with the source and drain regions, to epitaxially grow a first metal silicide; depositing a second metal layer on the first metal silicide; and performing a second annealing such that the second metal layer reacts with the first metal silicide as well as the source and drain regions, to form a second metal silicide. In accordance with the method for manufacturing a semiconductor device of the present invention, by means of epitaxially growing an ultra-thin metal silicide on the source and drain regions, the grain boundaries among silicide particles are minimized or eliminated, the metal diffusion speed and direction are limited, thus the lateral growth of the metal silicide is suppressed and the device performance is further increased.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括以下步骤：在衬底上形成栅叠层结构; 在栅极堆叠结构的两侧形成源极和漏极区域以及栅极间隔物; 在所述源区和漏区上沉积第一金属层; 进行第一退火，使得第一金属层与源区和漏区反应，以外延生长第一金属硅化物; 在第一金属硅化物上沉积第二金属层; 以及执行第二退火，使得所述第二金属层与所述第一金属硅化物以及所述源极和漏极区域反应，以形成第二金属硅化物。 根据本发明的半导体器件的制造方法，通过在源极和漏极区域外延生长超薄金属硅化物，硅化物粒子之间的晶界被最小化或消除，金属扩散速度和方向 受限，金属硅化物的横向生长受到抑制，器件性能进一步提高。

公开(公告)号：US20130273669A1

公开(公告)日：2013-10-17

申请号：US13698283

申请日：2012-06-12

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC: H01L21/306

CPC classification number: H01L21/30625 ,  H01L21/31053 ,  H01L21/31056 ,  H01L22/26 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.

Abstract translation: 本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二介电隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。 根据本发明的化学机械平面化方法的均匀性的方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差 并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

公开(公告)号：US20130213434A1

公开(公告)日：2013-08-22

申请号：US13497768

申请日：2011-11-28

Applicant: Guilei Wang ,  Junfeng Li ,  Chao Zhao

Inventor： Guilei Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02

CPC classification number: H01L21/02 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4404 ,  C23C16/505 ,  C23C16/56 ,  H01L21/76837

Abstract: A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

Abstract translation: 公开了一种用于消除接触孔工艺中的接触桥的方法，其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单，使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。 叠层自适应保护薄膜具有良好的粘合性，紧凑性和均匀性，以保护HDP CVD设备室的侧壁不被等离子体损坏，并避免产生缺陷颗粒，从而提高HDP CVD技术产量并消除 接触孔过程中的接触桥现象。

公开(公告)号：US08486805B2

公开(公告)日：2013-07-16

申请号：US13142757

申请日：2011-04-11

Applicant: Chao Zhao ,  Dapeng Chen ,  Wen Ou

Inventor： Chao Zhao ,  Dapeng Chen ,  Wen Ou

IPC: H01L21/30

CPC classification number: H01L21/76898 ,  H01L21/76224 ,  H01L2924/0002

Abstract: A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

Abstract translation: 提供了一种硅通孔及其形成方法。 该方法包括：提供半导体衬底，所述半导体衬底包括上表面和相对的下表面; 蚀刻半导体衬底的上表面以形成开口; 用导电材料填充开口以形成第一钉; 蚀刻半导体衬底的下表面以形成凹部，使得第一指甲暴露在凹部的底部; 用可蚀刻的导电材料填充凹部，并蚀刻可蚀刻的导电材料以形成第二钉，使得第二钉与第一钉垂直连接; 以及在所述第二钉和所述半导体衬底之间填充间隙以及所述第二钉和相邻的具有介电层的第二钉之间的间隙。 然后，本发明可以提高硅通孔的可靠性并避免空隙。

公开(公告)号：US08420492B2

公开(公告)日：2013-04-16

申请号：US13143591

申请日：2011-01-27

Applicant: Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7845

Abstract: The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.

Abstract translation: 本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。 本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。

公开(公告)号：US20130059435A1

公开(公告)日：2013-03-07

申请号：US13510730

申请日：2011-11-30

Applicant: Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

Inventor： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/51

Abstract: The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

Abstract translation: 本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。 根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。 它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。