公开(公告)号：US06998313B2

公开(公告)日：2006-02-14

申请号：US10733626

申请日：2003-12-11

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

公开(公告)号：US06900112B2

公开(公告)日：2005-05-31

申请号：US10426348

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A process for forming shallow trench isolation region with corner protection layer. A protection layer is formed within the opening that defines the isolation trench as part of the etching mask such that the etching rate of the protection layer is less than the mask layer and the pad insulating layer to the etchant used to remove the mask layer and pad insulating layer. The protection layer is partially removed and left adjacent to the shallow trench isolation region as a corner protection layer after removing the mask layer and pad insulating layer. Thus, the indentation next to the corner of the isolation region is avoided.

Abstract translation: 用于形成具有角保护层的浅沟槽隔离区的工艺。 在开口内形成保护层，其将隔离沟槽定义为蚀刻掩模的一部分，使得保护层的蚀刻速率小于用于去除掩模层和焊盘的掩模层和蚀刻剂的焊盘绝缘层 绝缘层。 在去除掩模层和焊盘绝缘层之后，保护层被部分地去除并且与作为转角保护层的浅沟槽隔离区相邻。 因此，避免了隔离区域的拐角附近的压痕。

公开(公告)号：US20050101090A1

公开(公告)日：2005-05-12

申请号：US11014483

申请日：2004-12-15

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L29/40114

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

Abstract translation: 具有多个尖端的浮动栅极及其制造方法。 提供半导体衬底，在其上形成图案化的硬掩模层，其中图案化的硬掩模层具有开口。 在开口的底部形成具有第一预定厚度的栅介质层和第一导电层。 间隔件形成在开口的侧壁上。 导电间隔件形成在间隔件的侧壁上。 第一导电层被蚀刻到第二预定厚度。 由第一导电层和导电间隔物提供多尖端浮栅。 在开口中形成保护层。 蚀刻图案化的硬掩模层，栅介质层，保护层的一部分和第一间隔物的一部分，以露出第一导电层的表面。

公开(公告)号：US06800526B2

公开(公告)日：2004-10-05

申请号：US10302865

申请日：2002-11-25

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

Abstract translation: 一种分离栅闪存单元的制造方法，包括以下步骤：在半导体衬底上形成有源区; 在半导体衬底上形成缓冲层; 在缓冲层上形成第一介电层; 去除所述第一电介质层的一部分; 定义一个开口 去除开口内的缓冲层; 形成栅绝缘层和浮栅; 在所述半导体衬底中形成源区; 在开口上沉积共形的第二介电层; 去除第一介电层和浮栅之外的缓冲层; 并形成氧化物层和控制栅极。

公开(公告)号：US06753223B2

公开(公告)日：2004-06-22

申请号：US10295260

申请日：2002-11-15

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

Abstract: A method for fabricating a flash memory cell. The method starts with sequential formation of a first insulating layer, a first conductive layer and pad layer on a semiconductor substrate. Part of the pad layer is removed to form a first opening, followed by forming a conductive spacer, i.e. the tip, on the sidewalls of the first opening. Then, parts of the pad layer, first conductive layer, first insulating layer and substrate are removed to form a second opening. Next, a second insulating layer is formed to fill the first opening and the second opening to form a first gate insulating layer and shallow trench isolation. The first gate insulating layer is used as hard mask to remove part of the first conductive layer and the first insulating layer to form a floating gate and a second insulating layer. Tunneling oxide and control gate are then formed on the floating gate. Finally, a source/drain is formed.

Abstract translation: 一种制造闪存单元的方法。 该方法从在半导体衬底上顺序形成第一绝缘层，第一导电层和焊盘层开始。 去除衬垫层的一部分以形成第一开口，随后在第一开口的侧壁上形成导电间隔物，即尖端。 然后，去除衬垫层，第一导电层，第一绝缘层和衬底的一部分以形成第二开口。 接下来，形成第二绝缘层以填充第一开口和第二开口，以形成第一栅极绝缘层和浅沟槽隔离。 第一栅绝缘层用作硬掩模以去除部分第一导电层和第一绝缘层，以形成浮栅和第二绝缘层。 然后在浮动栅上形成隧道化氧化物和控制栅极。 最后，形成源极/漏极。

公开(公告)号：US06673676B2

公开(公告)日：2004-01-06

申请号：US10229529

申请日：2002-08-27

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.

Abstract translation: 一种制造闪存单元的方法。 该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 在所述第一栅极绝缘层上形成第一导电层; 形成浮栅绝缘层; 通过将杂质离子注入衬底来形成源区; 形成第二绝缘层; 形成浮栅区域; 形成第三绝缘层; 在所述第三绝缘层上形成第二导电层; 在所述第二导电层上形成第四绝缘层; 形成浮栅区域; 在所述第三绝缘层上形成第二导电层; 形成第一侧壁间隔物; 形成控制栅极和隧道氧化物; 形成第二侧壁间隔物; 以及在所述衬底上形成漏区。

公开(公告)号：US5858835A

公开(公告)日：1999-01-12

申请号：US996193

申请日：1997-12-22

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L28/84

Abstract: A method for fabricating a capacitor over a semiconductor substrate is disclosed. The method includes the steps of: forming an insulating layer over the semiconductor substrate; forming a contact opening through the insulating layer to expose a portion of the semiconductor substrate; forming a first polysilicon layer over the insulating layer and filling in the contact opening to electrically contact the semiconductor substrate; patterning the first polysilicon layer to the insulating layer surface, thereby forming a trench for defining a capacitor region; forming a thin polysilicon layer with a rugged surface over the first polysilicon layer and the insulating layer; forming a mask layer over the thin polysilicon layer, wherein the mask layer has a smaller thickness in the trench bottom than in other regions; removing the mask layer in the trench bottom through an anisotropical etch step; removing the uncovered portions of the thin polysilicon layer to expose the insulating layer surface; removing the mask layer, thereby forming a storage electrode consisting of the thin polysilicon layer and the first polysilicon layer; forming a dielectric layer over the storage electrode and the exposed insulating layer; and forming a second polysilicon layer over the dielectric layer.

Abstract translation: 公开了一种在半导体衬底上制造电容器的方法。 该方法包括以下步骤：在半导体衬底上形成绝缘层; 形成通过所述绝缘层的接触开口以暴露所述半导体衬底的一部分; 在所述绝缘层上形成第一多晶硅层，并填充所述接触开口以电接触所述半导体衬底; 将第一多晶硅层图案化成绝缘层表面，从而形成用于限定电容器区域的沟槽; 在所述第一多晶硅层和所述绝缘层上形成具有凹凸表面的薄多晶硅层; 在所述薄多晶硅层上形成掩模层，其中所述掩模层在所述沟槽底部具有比在其它区域更小的厚度; 通过各向异性热蚀刻步骤去除沟槽底部中的掩模层; 去除所述薄多晶硅层的未覆盖部分以暴露所述绝缘层表面; 去除掩模层，从而形成由薄多晶硅层和第一多晶硅层组成的存储电极; 在所述存储电极和所述暴露的绝缘层上形成介电层; 以及在所述电介质层上形成第二多晶硅层。

公开(公告)号：US07476929B2

公开(公告)日：2009-01-13

申请号：US11269671

申请日：2005-11-09

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract translation: 本发明公开了一种具有间隔型浮动栅极的多位堆叠型非易失性存储器及其制造方法。 制造方法包括在半导体衬底上形成含有砷的图案化电介质层，其中图案化电介质层限定开口作为有效区域。 在图案化电介质层的侧壁上形成介质间隔物，并在半导体衬底上形成栅极电介质层。 源极/漏极区域通过使从扩散图案化的介电层扩散到半导体衬底中的热驱动方法形成。 间隔物形状的浮栅形成在电介质隔离物的侧壁和栅介电层上。 在间隔物形浮栅上形成层间绝缘层。 在层间电介质层上形成控制栅极，填充有源区的开口。

公开(公告)号：US20060063339A1

公开(公告)日：2006-03-23

申请号：US11269671

申请日：2005-11-09

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC: H01L21/331 ,  H01L21/8222

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract translation: 本发明公开了一种具有间隔型浮动栅极的多位堆叠型非易失性存储器及其制造方法。 制造方法包括在半导体衬底上形成含有砷的图案化电介质层，其中图案化电介质层限定开口作为有效区域。 在图案化电介质层的侧壁上形成介质间隔物，并在半导体衬底上形成栅极电介质层。 源极/漏极区域通过使从扩散图案化的介电层扩散到半导体衬底中的热驱动方法形成。 间隔物形状的浮栅形成在电介质隔离物的侧壁和栅介电层上。 在间隔物形浮栅上形成层间绝缘层。 在层间电介质层上形成控制栅极，填充有源区的开口。

公开(公告)号：US06818948B2

公开(公告)日：2004-11-16

申请号：US10621597

申请日：2003-07-16

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L2976

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A split gate flash memory device and method of fabricating the same. A cell of the split gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 一种分闸式闪存装置及其制造方法。 根据本发明的分裂栅极闪存器件的单元被布置在衬底内的单元沟槽中，以实现存储单元的更高集成度。