公开(公告)号：US07579859B2

公开(公告)日：2009-08-25

申请号：US11763077

申请日：2007-06-14

Applicant: Pei-Chun Liao ,  Chia-Lin Chen

Inventor： Pei-Chun Liao ,  Chia-Lin Chen

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/129 ,  G01R31/2623

Abstract: The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, the second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage.

Abstract translation: 本发明提供一种由于时间依赖介电击穿（TDDB）确定半导体器件的寿命的方法。 该方法包括提供设置为MOS晶体管的栅介质层的介质层的多个样本，其近似源/漏电流密度分布作为施加在样本上的电压的第一函数，将基板电流密度分布近似为第二 作为施加在样品上的电压的函数，近似作为源/漏电流密度和样品中的衬底电流密度的第三函数的介电层寿命分布，从第一，第二和第三函数导出经验模型，其中 介电层寿命是施加在其上的电压的函数，并且使用该模型来确定在预定的工作栅极电压下的介电层寿命。

公开(公告)号：US20080318378A1

公开(公告)日：2008-12-25

申请号：US11765971

申请日：2007-06-20

Applicant: Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

Inventor： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract translation: 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

公开(公告)号：US07453280B1

公开(公告)日：2008-11-18

申请号：US11896364

申请日：2007-08-31

Applicant: Sheng-Hui Liang ,  Chia-Lin Chen ,  Pei-Chun Liao ,  Chin-Yuan Ko

Inventor： Sheng-Hui Liang ,  Chia-Lin Chen ,  Pei-Chun Liao ,  Chin-Yuan Ko

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2623 ,  G01R31/2831 ,  G01R31/2894 ,  G11C11/41 ,  G11C29/006 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.

Abstract translation: 提供了一种用于测试晶片级的一批半导体器件的方法。 该方法包括以下步骤：（a）获得每个半导体器件的栅极电介质的击穿电压; （b）向每个半导体器件的栅极电介质施加低于击穿电压但高于半导体器件的栅极电介质的基极电压的应力电压; （c）在步骤（b）之后，测量每个半导体器件在基极电压下的栅极电介质的电流; 和（d）从测量的电流获得拖尾分布。

公开(公告)号：US07316970B2

公开(公告)日：2008-01-08

申请号：US10892014

申请日：2004-07-14

Applicant: Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/425

CPC classification number: H01L21/31111 ,  H01L21/823481 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

Abstract translation: 在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。 在半导体衬底上形成隔离结构。 在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。 形成光致抗蚀剂掩模以部分覆盖原始氮化物层。 执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。 因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

公开(公告)号：US20060049470A1

公开(公告)日：2006-03-09

申请号：US10936271

申请日：2004-09-07

Applicant: Chia-Lin Chen ,  Ming-Jie Huang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Ming-Jie Huang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L29/76

CPC classification number: H01L29/4925 ,  H01L21/28035 ,  H01L29/665

Abstract: A method for forming a microelectronic product and the microelectronic product resulting from the method both employ a bilayer gate electrode. The bilayer gate electrode employs: (1) a first layer formed of a random oriented polycrystalline silicon material; and (2) a second layer laminated to the first layer and formed of a columnar oriented polycrystalline silicon material. The gate electrode provides enhanced performance to a semiconductor device within which it is formed.

Abstract translation: 形成微电子产物的方法和由该方法得到的微电子产物都采用双层栅电极。 双层栅极采用：（1）由随机取向的多晶硅材料形成的第一层; 和（2）层压到第一层并由柱状取向的多晶硅材料形成的第二层。 栅电极为其形成的半导体器件提供增强的性能。

公开(公告)号：US20050242376A1

公开(公告)日：2005-11-03

申请号：US10834474

申请日：2004-04-29

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

IPC: H01L21/336 ,  H01L21/338 ,  H01L21/76 ,  H01L29/745 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

Abstract: A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.

Abstract translation: 半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。 该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿法蚀刻速率。

公开(公告)号：US20050186750A1

公开(公告)日：2005-08-25

申请号：US10785524

申请日：2004-02-24

Applicant: Kuen-Chyr Lee ,  Liang-Gi Yao ,  Tien-Chih Chang ,  Chia-Lin Chen ,  Shih-Chang Chen ,  Mong-Song Liang

Inventor： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Tien-Chih Chang ,  Chia-Lin Chen ,  Shih-Chang Chen ,  Mong-Song Liang

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L21/8222

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532

Abstract: A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, and then growing an epitaxial Si—Ge layer with a Si pap layer at a lower temperature to form the intrinsic base with low boron out-diffusion. This results in an HBT having the desired narrow base profile while minimizing the discontinuities (voids) in the Si—Ge layer over the insulator to provide good electrical contacts and uniformity to the intrinsic base.

Abstract translation: 在异质结双极晶体管的基极的基板上制造改进的硅 - 锗层的方法是使用双温工艺实现的。 该方法包括在较高温度下生长种子层以在较短的反应时间下降低晶粒尺寸，然后在较低温度下生长具有Si pap层的外延Si-Ge层以形成具有低硼外扩散的本征碱 。 这导致HBT具有期望的窄基底轮廓，同时最小化绝缘体上的Si-Ge层中的不连续性（空隙），以提供良好的电接触和对本征基底的均匀性。

公开(公告)号：US20050037555A1

公开(公告)日：2005-02-17

申请号：US10870878

申请日：2004-06-17

Applicant: Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/76

CPC classification number: H01L21/28044 ,  C23C16/24 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28052 ,  H01L29/4925

Abstract: A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.

Abstract translation: 提供了具有随机晶粒多晶硅层的半导体器件及其制造方法。 在一个示例中，该器件在衬底上包括半导体衬底和绝缘体层。 具有随机晶粒结构的第一多晶硅层位于绝缘体层的上方，半导体合金层位于第一多晶硅层的上方，第二多晶硅层位于半导体合金层的上方。

公开(公告)号：US07361572B2

公开(公告)日：2008-04-22

申请号：US11059728

申请日：2005-02-17

Applicant: Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/76

CPC classification number: H01L21/76235

Abstract: A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.

Abstract translation: 公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。 根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。 该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化 的衬里氧化物层。 本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

公开(公告)号：US20080073724A1

公开(公告)日：2008-03-27

申请号：US11534536

申请日：2006-09-22

Applicant: Sheng-Hui Liang ,  Chia-Lin Chen ,  Chin-Yuan Ko

Inventor： Sheng-Hui Liang ,  Chia-Lin Chen ,  Chin-Yuan Ko

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L27/092 ,  H01L29/7843

Abstract: A semiconductor device and a method for forming the same provides a double layer contact etch stop layer selectively formed over PMOS transistors with only a single silicon nitride contact etch stop layer formed over NMOS transistors on the same chip. The composite contact etch stop layer structure formed over the PMOS transistor avoids data retention and plasma induced damage issue associated with the PMOS transistor and a single silicon nitride contact etch stop layer formed over NMOS transistors avoids device shifting issues.

Abstract translation: 半导体器件及其形成方法提供了选择性地形成在PMOS晶体管上的双层接触蚀刻停止层，其中在同一芯片上的NMOS晶体管上形成仅一个氮化硅接触蚀刻停止层。 在PMOS晶体管上形成的复合接触蚀刻停止层结构避免了与PMOS晶体管相关联的数据保持和等离子体引起的损伤问题，并且在NMOS晶体管上形成的单个氮化硅接触蚀刻停止层避免了器件移位问题。