公开(公告)号：US07920406B2

公开(公告)日：2011-04-05

申请号：US12180586

申请日：2008-07-28

Applicant: Geoffrey W. Burr ,  Kailash Gopalakrishnan

Inventor： Geoffrey W. Burr ,  Kailash Gopalakrishnan

IPC: G11C11/00 ,  G11C5/06

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  G11C2216/10

Abstract: A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.

Abstract translation: 一种用于形成存储器结构的方法，包括：形成布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元还包括能够被编程为多个电阻状态的电阻性存储器件 每个电阻存储器件在其第一端处耦合到位线之一; 在其第二端配置与每个所述电阻式存储器件串联的整流元件; 配置与每个单独存储器单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及形成公共连接，其被配置为沿着字线方向将两个或更多个组的相邻整流装置短路在一起。

公开(公告)号：US20100248441A1

公开(公告)日：2010-09-30

申请号：US12794826

申请日：2010-06-07

Applicant: Kailash Gopalakrishnan ,  Rohit Sudhir Shenoy

Inventor： Kailash Gopalakrishnan ,  Rohit Sudhir Shenoy

IPC: H01L21/425 ,  H01L21/20

CPC classification number: H01L27/0207 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42336 ,  H01L29/785 ,  Y10S438/947 ,  Y10S977/888 ,  Y10S977/936

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract translation: 一种结构，使用该结构的存储器件以及该结构的制造方法。 该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中， 每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此交错; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二共同接触点 在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。

公开(公告)号：US20080314738A1

公开(公告)日：2008-12-25

申请号：US11765142

申请日：2007-06-19

Applicant: Kailash Gopalakrishnan ,  David B. Mitzi ,  Rohit S. Shenoy

Inventor： Kailash Gopalakrishnan ,  David B. Mitzi ,  Rohit S. Shenoy

IPC: C25B9/06 ,  B05D5/12 ,  H01L21/64

CPC classification number: H01L45/142 ,  C23C18/1204 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/1608

Abstract: The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.

Abstract translation: 本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。 无定形硫族化物固体活性电解质层位于第一和第二金属层之间。 无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的， 将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。 本公开还涉及制造固体电解质器件的方法。

公开(公告)号：US20080232160A1

公开(公告)日：2008-09-25

申请号：US12110644

申请日：2008-04-28

Applicant: KAILASH GOPALAKRISHNAN

Inventor： KAILASH GOPALAKRISHNAN

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L27/2409 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/224

Abstract: An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance in the ON state (because it is a metallic filament in the ON state). These attributes make it a near ideal diode. During the passage of current (during program/read/erase) of the memory element, the solid electrolyte material also programs into the low resistance state. The final state of the solid electrolyte material is reverted to a high resistance state while making sure that the final state of the memory material is the one desired.

Abstract translation: 描述了一种不对称编程的记忆材料（例如固体电解质材料），用作整流元件，用于驱动交叉点存储器架构中的对称或基本对称的电阻性存储器元件。 固体电解质元件（SE）在OFF状态下具有非常高的电阻，并且在ON状态下具有非常低的电阻（因为它是处于ON状态的金属灯丝）。 这些属性使其成为接近理想的二极管。 在存储元件的电流（在编程/读取/擦除期间）期间，固体电解质材料也编程成低电阻状态。 固体电解质材料的最终状态被还原成高电阻状态，同时确保记忆材料的最终状态是期望的。

公开(公告)号：US20080225578A1

公开(公告)日：2008-09-18

申请号：US12055907

申请日：2008-03-26

Applicant: Geoffrey W. Burr ,  Kailash Gopalakrishnan

Inventor： Geoffrey W. Burr ,  Kailash Gopalakrishnan

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  G11C2216/10

Abstract: A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.

Abstract translation: 存储器结构包括：布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元进一步包括能够被编程为多个电阻状态的电阻性存储器件，每个电阻状态 在其第一端耦合到位线中的一个的存储器件; 整流元件，其每个电阻存储器件在其第二端处串联; 与每个单独的存储单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及公共连接，其被配置为沿着字线方向以两个或更多个组的形式将相邻整流装置短路。

公开(公告)号：US20080068065A1

公开(公告)日：2008-03-20

申请号：US11926031

申请日：2007-10-28

Applicant: Hemantha Wickramasinghe ,  Kailash Gopalakrishnan

Inventor： Hemantha Wickramasinghe ,  Kailash Gopalakrishnan

IPC: H03K17/00

CPC classification number: H01L27/1203 ,  G11C16/08 ,  H01L21/84 ,  H01L27/115 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

公开(公告)号：US20080054306A1

公开(公告)日：2008-03-06

申请号：US11468512

申请日：2006-08-30

Applicant: Kailash Gopalakrishnan ,  Rohit Sudhir Shenoy

Inventor： Kailash Gopalakrishnan ,  Rohit Sudhir Shenoy

IPC: H01L27/10

CPC classification number: H01L27/228 ,  G11C13/0004 ,  H01L21/84 ,  H01L27/24 ,  H01L29/785

Abstract: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.

公开(公告)号：US20060244058A1

公开(公告)日：2006-11-02

申请号：US11117276

申请日：2005-04-27

Applicant: Hemantha Wickramasinghe ,  Kailash Gopalakrishnan

Inventor： Hemantha Wickramasinghe ,  Kailash Gopalakrishnan

IPC: H01L29/76

CPC classification number: H01L27/1203 ,  G11C16/08 ,  H01L21/84 ,  H01L27/115 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

公开(公告)号：US20060244047A1

公开(公告)日：2006-11-02

申请号：US11116700

申请日：2005-04-27

Applicant: Kailash Gopalakrishnan ,  Hemantha Wickramasinghe

Inventor： Kailash Gopalakrishnan ,  Hemantha Wickramasinghe

IPC: H01L29/788

CPC classification number: H01L27/115 ,  G11C16/08 ,  H01L21/84 ,  H01L27/1203

Abstract: A memory device or a logic device that uses an electronically scannable multiplexing device capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract translation: 一种存储器件或逻辑器件，其使用能够寻址易失性或非易失性存储器单元内的多个位的电子扫描复用器件。 多路复用装置产生具有两个相对形成的耗尽区的电子扫描导电通道。 每个耗尽区的耗尽宽度由施加到多路复用器件每端的相应控制栅极的电压控制。 目前的多位寻址技术允许例如在单个节点上访问或寻址10到100位的数据。 本发明还可用于构建可编程纳米尺度逻辑阵列或用于随机访问纳米级传感器阵列。

公开(公告)号：US08902690B2

公开(公告)日：2014-12-02

申请号：US13584423

申请日：2012-08-13

Applicant: Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

Inventor： Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC: G11C8/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/004 ,  G11C2213/71 ,  G11C2213/72

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

Abstract translation: 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。