公开(公告)号：US20040179410A1

公开(公告)日：2004-09-16

申请号：US10813038

申请日：2004-03-31

Applicant: Renesas Technology Corp.

Inventor： Yuuichi Hirano ,  Takashi Ipposhi

IPC: G11C011/34

CPC classification number: G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

Abstract: A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors (Q1, Q4) are driver transistors, NMOS transistors (Q3, Q6) are access transistors, and PMOS transistors (Q2, Q5) are load transistors. An NMOS transistor (Q7) is a transistor for adding a resistance. The NMOS transistor (Q7) has its gate connected to a power supply (1). The NMOS transistor (Q7) has one of its source and drain connected to a storage node (ND1) and the other connected to the gates of the NMOS transistor (Q4) and the PMOS transistor (Q5). The resistance between the source and drain of the NMOS transistor (Q7) can be adjusted with the gate length, the gate width, the source/drain impurity concentration, etc., which is, for example, about several tens of kilohms (knull).

Abstract translation: 获得具有高软误差抗扰度的半导体存储装置。 半导体存储装置具有SRAM存储单元。 NMOS晶体管（Q1，Q4）是驱动晶体管，NMOS晶体管（Q3，Q6）是存取晶体管，PMOS晶体管（Q2，Q5）是负载晶体管。 NMOS晶体管（Q7）是用于增加电阻的晶体管。 NMOS晶体管（Q7）的栅极连接到电源（1）。 NMOS晶体管（Q7）的源极和漏极之一连接到存储节点（ND1），另一个连接到NMOS晶体管（Q4）和PMOS晶体管（Q5）的栅极。 NMOS晶体管（Q7）的源极和漏极之间的电阻可以通过栅极长度，栅极宽度，源极/漏极杂质浓度等进行调整，例如约几十千赫兹（kOmega） 。

公开(公告)号：US20040178485A1

公开(公告)日：2004-09-16

申请号：US10687095

申请日：2003-10-17

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Tomokazu Otani ,  Jun Nakai

IPC: H01L023/02

CPC classification number: H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes a plurality of semiconductor elements each having a plurality of arranged pads, and the semiconductor elements are stacked and housed in the semiconductor device. The semiconductor device further includes a power supply frame that is bar-shaped and supplies a power voltage to at least two of the plurality of semiconductor elements.

Abstract translation: 半导体器件包括多个半导体元件，每个半导体元件具有多个布置的焊盘，并且半导体元件堆叠并容纳在半导体器件中。 半导体器件还包括棒状的电源框架，并将电源电压提供给多个半导体元件中的至少两个。

公开(公告)号：US20040174764A1

公开(公告)日：2004-09-09

申请号：US10768036

申请日：2004-02-02

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Hideto Matsuoka ,  Hideyuki Noda

IPC: G11C005/00

CPC classification number: G11C29/816 ,  G11C15/00 ,  G11C15/04 ,  G11C15/043 ,  G11C29/848

Abstract: A shift information latch circuit includes a plurality of latch portions provided corresponding to memory cell rows, respectively, and a fuse circuit transmitting fuse data produced corresponding to an address of a faulty memory cell row. The plurality of latch portion successively receive fuse data, and each transmit a shift control signal instructing a shift operation. In response to this shift control signal, a row decoder and a match line amplifier execute a shift operation for repairing the faulty memory cell row. In this structure, a decoder circuit decoding the address of the faulty memory cell row is not arranged so that a whole area of the circuits executing the shift operation is reduced, and the shift operation can be easily executed.

Abstract translation: 移位信息锁存电路分别包括对应于存储单元行提供的多个锁存部分，以及熔丝电路，其传输对应于故障存储单元行的地址产生的熔丝数据。 多个锁存部分依次接收熔丝数据，并且发送指示换档操作的换档控制信号。 响应于该移位控制信号，行解码器和匹配线放大器执行用于修复故障存储单元行的移位操作。 在这种结构中，解码电路故障存储单元行地址的译码器电路不被排列，从而减少执行移位操作的电路的整个区域，并且可以容易地执行移位操作。

公开(公告)号：US20040174742A1

公开(公告)日：2004-09-09

申请号：US10796995

申请日：2004-03-11

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Motoki Kanamori ,  Takayuki Tamura ,  Kenji Kozakai ,  Atsushi Shikata ,  Shinsuke Asari

IPC: G11C011/34

CPC classification number: G11C16/10 ,  G11C2207/229

Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.

公开(公告)号：US20040171239A1

公开(公告)日：2004-09-02

申请号：US10608338

申请日：2003-06-30

Applicant: Renesas Technology Corp.

Inventor： Tomohiro Tanaka ,  Naofumi Murata ,  Tohru Koyama

IPC: H01L021/22

CPC classification number: H01L28/40 ,  H01L21/0276 ,  H01L21/3144 ,  H01L21/76838 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: For the formation of a first aluminum interconnect line (3) serving as a lower electrode of a MIM capacitor element, an antireflection film (4) having a two-layer structure of a TiN layer (41) and a SiON layer (42) is used. The SiON layer (42) of the antireflection film (4) is utilized as-is as a dielectric layer of the MIM capacitor element. An upper electrode (81) and a contact plug (82) are formed by the same process. Since the upper surfaces of the upper electrode (81) and the contact plug (82) are at the same level, an electrical contact can be easily provided between a second aluminum interconnect line (10) and each of the upper electrode (81) and the lower electrode (first aluminum interconnect line (3)) of the MIM capacitor element. Accordingly, the MIM capacitor element and contacts to the upper and lower electrodes of the MIM capacitor element can be formed through simple processes.

Abstract translation: 为了形成用作MIM电容器元件的下电极的第一铝互连线（3），具有TiN层（41）和SiON层（42）的两层结构的抗反射膜（4）是 用过的。 抗反射膜（4）的SiON层（42）被用作MIM电容器元件的电介质层。 通过相同的工艺形成上电极（81）和接触插塞（82）。 由于上部电极（81）和接触插塞（82）的上表面处于同一水平，所以可以容易地在第二铝互连线（10）与上电极（81）和 MIM电容器元件的下电极（第一铝互连线（3））。 因此，可以通过简单的工艺形成MIM电容器元件和与MIM电容器元件的上下电极的接触。

公开(公告)号：US20040171225A1

公开(公告)日：2004-09-02

申请号：US10795377

申请日：2004-03-09

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Motoshige Igarashi

IPC: H01L021/8238 ,  H01L021/336 ,  H01L021/3205 ,  H01L021/4763

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/6653

Abstract: A gate insulating film is formed on a semiconductor substrate, and a gate electrode is formed by deposition of semiconductor material on the gate insulating film. An amorphous layer is then formed along the surface of or inside the gate electrode, and side walls are formed on the gate electrode. Finally, impurities are implanted into the semiconductor substrate by ion implantation while the gate electrode and the side walls are used as masks.

Abstract translation: 在半导体衬底上形成栅极绝缘膜，并且通过在栅极绝缘膜上沉积半导体材料形成栅电极。 然后沿着栅电极的表面或内部形成非晶层，并且在栅电极上形成侧壁。 最后，通过离子注入将杂质注入到半导体衬底中，同时将栅电极和侧壁用作掩模。

公开(公告)号：US20040170387A1

公开(公告)日：2004-09-02

申请号：US10677228

申请日：2003-10-03

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Yoshinori Matsuura ,  Hiroshi Segawa

IPC: H04N005/76

CPC classification number: H04N21/2368 ,  H04N21/23406 ,  H04N21/234318 ,  H04N21/4341 ,  H04N21/44004

Abstract: A time zone start time point calculating unit calculates a time zone to be set in a VOBU in accordance with audio bit rate. A time zone comparing unit compares a time point at which an audio pack is to be multiplexed with the time zone calculated by the time zone start time point calculating unit. A flag setting unit sets whether the audio pack is to be completed or not in accordance with the result of comparison by the time zone comparing unit. Therefore, a completing process takes place before a VOBU boundary, and a completed PCK will not be generated immediately after the VOBU boundary. Thus, generation of a buffer overflow can be prevented.

Abstract translation: 时区开始时刻计算单元根据音频比特率计算要设置在VOBU中的时区。 时区比较单元将音频包与多路复用的时间点与由时区开始时间点计算单元计算的时区进行比较。 标志设置单元根据时区比较单元的比较结果来设置是否要完成音频包。 因此，在VOBU边界之前进行完成处理，并且在VOBU边界之后不会立即生成完成的PCK。 因此，可以防止产生缓冲器溢出。

公开(公告)号：US20040169228A1

公开(公告)日：2004-09-02

申请号：US10619431

申请日：2003-07-16

Applicant: Renesas Technology Corp.

Inventor： Motoi Ashida ,  Takashi Terada

IPC: H01L027/01

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with a CMOS transistor structure in which a gate electrode and a wire connecting an Nnull-type active region and a Pnull-type active region overlap each other in plan view, to reduce a footprint of the CMOS transistor structure, is provided. An Nnull-type active region (1) of an n-channel MOS transistor and a Pnull-type active region (2) of a p-channel MOS transistor are formed in a surface portion of a semiconductor substrate by ion implantation or the like. Gate electrodes (3) are formed on the Nnull-type active region (1) and the Pnull-type active region (2). Insulating films (4, 5) of silicon nitride are formed on the gate electrodes (3). An interlayer insulating film (6) of silicon oxide is formed over the gate electrodes (3) covered with the insulating films (4, 5), by CVD or the like. Openings (7) for accommodating wires connecting the Nnull-type active region (1) and the Pnull-type active region (2) are formed in the interlayer insulating film (6). A metal film such as an aluminum film is buried in the openings (7), to form buried wires (8).

Abstract translation: 具有CMOS晶体管结构的半导体器件，其中栅极电极和连接N +型有源区和P +型有源区的导线在平面图中彼此重叠，以减少CMOS的占空比 晶体管结构。 在沟道MOS晶体管的n沟道MOS晶体管和P +型有源区（2）中的N +型有源区（1）形成在半导体衬底的表面部分 离子注入等。 栅电极（3）形成在N +型有源区（1）和P +型有源区（2）上。 在栅电极（3）上形成氮化硅绝缘膜（4,5）。 通过CVD等在绝缘膜（4,5）覆盖的栅电极（3）上形成氧化硅层间绝缘膜（6）。 用于容纳连接N +型有源区（1）和P +型有源区（2）的导线的开口（7）形成在层间绝缘膜（6）中。 将诸如铝膜的金属膜掩埋在开口（7）中，以形成掩埋线（8）。

公开(公告)号：US20040168127A1

公开(公告)日：2004-08-26

申请号：US10667354

申请日：2003-09-23

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

IPC: G06F017/21

CPC classification number: G06T1/60 ,  G06T3/40

Abstract: When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Abstract translation: 当由行数计数单元计数的行号对应于规定行号时，传送源地址产生单元将偏移地址设置单元中设置的偏移地址添加到各个传送源地址，作为地址输出到存储器。 DMA控制单元根据由传送源地址生成单元生成的传送源地址和由传送目的地地址生成单元生成的传送目的地地址进行DMA传送。 因此，图像数据的快速放大/缩小成为可能。

公开(公告)号：US20040167755A1

公开(公告)日：2004-08-26

申请号：US10630775

申请日：2003-07-31

Applicant: Renesas Technology Corp.

Inventor： Kazuya Kamon

IPC: G06F017/10

CPC classification number: B24B37/042 ,  G06F17/5022 ,  G06F2217/12 ,  H01L21/67253 ,  Y02P90/265

Abstract: A simulator is provided which can simulate in consideration of various parameters in a CMP process. A pattern density two-dimensional distribution calculating part takes a pattern density two-dimensional distribution image. A mesh adjusting part performs a mesh adjustment of a measured data. A height distribution calculating part calculates a height distribution based on the pattern density two-dimensional distribution image. A correlation coefficient calculating part calculates a correlation coefficient by performing a least squares analysis of a measured data and a height distribution data. Passing through a Fourier calculation part, spatial filter part, and reverse Fourier calculating part, the pattern density two-dimensional distribution image becomes a pattern density two-dimensional distribution image. This distribution image further passes through a height distribution calculating part, resulting in a height distribution data. The correlation coefficient calculating part calculates a correlation coefficient by performing a least squares analysis of the height distribution data and measured data after CMP process.

Abstract translation: 提供了可以在CMP过程中考虑各种参数来模拟的模拟器。 图案密度二维分布计算部分采用图案密度二维分布图像。 网格调整部分执行测量数据的网格调整。 高度分布计算部分基于图案密度二维分布图像来计算高度分布。 相关系数计算部分通过对测量数据和高度分布数据进行最小平方分析来计算相关系数。 通过傅里叶计算部分，空间滤波器部分和反傅立叶计算部分，图案密度二维分布图像变为图案密度二维分布图像。 该分布图像进一步通过高度分布计算部，得到高度分布数据。 相关系数计算部通过对CMP处理后的高度分布数据和测量数据进行最小二乘法分析来计算相关系数。