公开(公告)号：US20250117559A1

公开(公告)日：2025-04-10

申请号：US18481866

申请日：2023-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankush Ankush ,  Venkateswaran Padmanabhan ,  Aayush Garg ,  Guha Lakshmanan ,  Avishek Pal

IPC: G06F30/3308

Abstract: A method comprises creating an electronic circuit design having a plurality of electronic components, simulating operation of the electronic circuit design, and creating a behavior model of the electronic circuit design. The method further comprises eliminating one or more data points created in the behavior model to generate a trimmed behavior model, generating a real number model based on the trimmed behavior model, the real number model comprising a plurality of weights, and generating a simulation model based on the plurality of weights.

公开(公告)号：US20250117338A1

公开(公告)日：2025-04-10

申请号：US18984278

申请日：2024-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad WU

IPC: G06F12/1027

Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

公开(公告)号：US20250117326A1

公开(公告)日：2025-04-10

申请号：US18987237

申请日：2024-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F12/02

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed data segments into faster access memory. The technique creates shadow copies of the most frequently accessed data segments in the faster access memory, which is associated with lower latency. Access frequencies of the data segments for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.

公开(公告)号：US12273541B2

公开(公告)日：2025-04-08

申请号：US18409147

申请日：2024-01-10

Applicant: Texas Instruments Incorporated

Inventor： Minhua Zhou

IPC: H04N19/176 ,  H04N19/119 ,  H04N19/13 ,  H04N19/147 ,  H04N19/15 ,  H04N19/174 ,  H04N19/50

Abstract: A method for encoding a video sequence is provided that includes signaling in the compressed bit stream that a subset of a plurality of partitioning modes is used for inter-prediction of a portion of the video sequence, using only the subset of partitioning modes for prediction of the portion of the video sequence, and entropy encoding partitioning mode syntax elements corresponding to the portion of the video sequence, wherein at least one partitioning mode syntax element is binarized according to a pre-determined binarization corresponding to the subset of partitioning modes, wherein the pre-determined binarization differs from a pre-determined binarization for the least one partitioning mode syntax element that would be used if the plurality of partitioning modes is used for inter-prediction.

公开(公告)号：US12273516B2

公开(公告)日：2025-04-08

申请号：US18361294

申请日：2023-07-28

Applicant: Texas Instruments Incorporated

Inventor： Minhua Zhou

IPC: H04N19/119 ,  H04N19/157 ,  H04N19/172

Abstract: A method for encoding a picture of a video sequence in a bit stream that constrains tile processing overhead is provided. The method includes computing a maximum tile rate for the video sequence, computing a maximum number of tiles for the picture based on the maximum tile rate, and encoding the picture wherein a number of tiles used to encode the picture is enforced to be no more than the maximum number of tiles.

公开(公告)号：US12273104B2

公开(公告)日：2025-04-08

申请号：US18115657

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Sovan Ghosh ,  Visvesvaraya Appala Pentakota

IPC: H03K5/01 ,  H03K17/687 ,  H03K5/00 ,  H03M1/12

Abstract: An example apparatus includes a first transistor configured to receive an analog voltage signal; a second transistor configured to receive a first control signal, coupled to the first transistor, and coupled to a first terminal; a third transistor configured to receive a second control signal, receive a supply voltage, and coupled to the first terminal; a capacitor coupled to the first terminal and to ground; a fourth transistor configured to receive a third control signal and coupled to the first terminal; a fifth transistor gate configured to receive a bias voltage, coupled to ground, and coupled to the fourth transistor; a sixth transistor coupled to the fourth transistor and to ground; a seventh transistor configured to receive the supply voltage, coupled to the first terminal and to the sixth transistor; and an eighth transistor coupled to the first terminal, to the sixth transistor, and to ground.

公开(公告)号：US12273099B2

公开(公告)日：2025-04-08

申请号：US18323987

申请日：2023-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tuli Dake

IPC: H03K17/0812 ,  H03K3/017 ,  H03K3/3565 ,  H03K19/0944

Abstract: A driver includes a first pre-driver having a first drive strength programming input and a first output, a first transistor having a first transistor control input coupled to the first output, and a second pre-driver having a second drive strength programming input and a second output. The driver also includes a second transistor having a second transistor control input coupled to the second output. The second transistor is coupled to the first transistor and to a driver output terminal. A circuit is coupled between the driver output terminal and the first drive strength programming input and between the driver output terminal and the second drive strength programming input.

公开(公告)号：US12272626B2

公开(公告)日：2025-04-08

申请号：US17683074

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Anindya Poddar

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.

公开(公告)号：US12271314B2

公开(公告)日：2025-04-08

申请号：US18508356

申请日：2023-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson ,  Neelima Muralidharan

IPC: G06F12/0808 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

公开(公告)号：US12271289B2

公开(公告)日：2025-04-08

申请号：US18403293

申请日：2024-01-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Kowkutla ,  Raghavendra Santhanagopal ,  Chunhua Hu ,  Anthony Frederick Seely ,  Nishanth Menon ,  Rajesh Kumar Vanga ,  Rejitha Nair ,  Siva Srinivas Kothamasu ,  Kazunobu Shin ,  Jason Peck ,  John Apostol

IPC: G06F9/44 ,  G06F9/4401 ,  G06F11/30 ,  G06F11/362 ,  G06F13/10

Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.