公开(公告)号：US09142641B1

公开(公告)日：2015-09-22

申请号：US14516545

申请日：2014-10-16

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308

CPC classification number: H01L29/6656 ,  H01L21/022 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/31116 ,  H01L29/66795

Abstract: A method for manufacturing a FinFET includes forming a merging spacer, through a plurality of sidewall pattern-transferring processes, and modifying a first interval between adjacent first mandrels as shorter than twice of thicknesses of a nitride layer, which is formed on the first mandrels and contoured thereto, followed by a first spacer being formed on a sidewall thereof, so that a FinFET composed of a plurality of fin-shaped structures having a non-integral multiple of pitches as well as an integral multiple of pitches can be manufactured.

Abstract translation: 一种用于制造FinFET的方法包括：通过多个侧壁图案转移工艺形成合并间隔物，并且修改相邻的第一心轴之间的第一间隔，其长度小于形成在第一心轴上的氮化物层的厚度的两倍， 然后在其侧壁上形成第一间隔物，从而可以制造由具有非整数倍的间距的多个鳍状结构构成的FinFET以及整数倍的间距。

公开(公告)号：US09135389B2

公开(公告)日：2015-09-15

申请号：US14035952

申请日：2013-09-25

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung Chen

IPC: G06F17/50 ,  H01L25/00 ,  H01L23/522 ,  H03K19/177

CPC classification number: G06F1/10 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/62 ,  G06F2217/84 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1774 ,  H01L2924/00

Abstract: A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a clock source and a sequential logic cell is provided. Then, at least one non-active wire delay module is inserted in the timing path to approach a predetermined clock arrival time. An integrated circuit structure utilizing the clock transmission adjusting method is also provided.

Abstract translation: 提供了一种适用于集成电路设计的时钟传输调整方法。 时钟传输调整方法包括以下步骤。 首先，提供包括时钟源和顺序逻辑单元的定时路径。 然后，在定时路径中插入至少一个非有效的线延迟模块以接近预定的时钟到达时间。 还提供了利用时钟传输调整方法的集成电路结构。

公开(公告)号：US20150255307A1

公开(公告)日：2015-09-10

申请号：US14722174

申请日：2015-05-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Hsien LIN ,  Hsin-Fu HUANG ,  Chi-Mao HSU ,  Chin-Fu LIN ,  Chun-Yuan WU

IPC: H01L21/311 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

Abstract translation: 提供蚀刻停止层的制造工艺。 制造方法包括提供基板的步骤; 在所述衬底上形成栅极叠层结构，其中所述栅极堆叠结构至少包括虚设多晶硅层和阻挡层; 去除所述虚设多晶硅层以限定沟槽并暴露所述阻挡层的表面; 在阻挡层的表面和沟槽的内壁上形成修复层; 以及在修复层上形成蚀刻停止层。 此外，具有蚀刻停止层的栅极堆叠结构的制造工艺还包括在沟槽内的蚀刻停止层上形成N型功函数金属层，并且在N型功函数金属上形成栅极层 沟内的层。

公开(公告)号：US20150129977A1

公开(公告)日：2015-05-14

申请号：US14074727

申请日：2013-11-08

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yu-Chun CHEN ,  Chang-Tzu Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0277

Abstract: A semiconductor electrostatic discharge (ESD) protection apparatus comprises at least one elementary transistor with a first conductivity type, a well region with a second conductivity type, a guard ring with the second conductivity type and a semiconductor interval region. The elementary transistor is formed in the well region. The guard ring surrounds the at least one elementary transistor. The semiconductor interval region is disposed between the elementary transistor and the guard ring in order to surrounds the elementary transistor, wherein the semiconductor interval region is an undoped region, a doped region with the first conductivity type or a doped region with the second conductivity type that has a doping concentration substantially less than that of the well region.

Abstract translation: 半导体静电放电（ESD）保护装置包括至少一个具有第一导电类型的基本晶体管，具有第二导电类型的阱区，具有第二导电类型的保护环和半导体间隔区。 在阱区中形成基本晶体管。 保护环围绕至少一个基本晶体管。 半导体间隔区域设置在基本晶体管和保护环之间以包围基本晶体管，其中半导体间隔区域是未掺杂区域，具有第一导电类型的掺杂区域或具有第二导电类型的掺杂区域， 具有显着小于阱区的掺杂浓度的掺杂浓度。

公开(公告)号：US20150048486A1

公开(公告)日：2015-02-19

申请号：US13968392

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hung-Lin Shih ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chieh-Wen Lo

IPC: H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0692 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/308 ,  H01L21/823821 ,  H01L29/06 ,  H01L29/66795

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract translation: 制造空间半导体结构的方法包括以下步骤。 首先，提供半导体衬底。 然后，在半导体衬底上形成第一掩模层。 然后，在第一掩模层中至少形成第一开口并暴露半导体衬底的一部分表面。 然后，在第一开口中形成第一半导体图形。 然后，在第一半导体图案和第一掩模层上形成第二掩模层。 然后，通过第二掩模层形成至少第二开口到第一掩模层，并暴露半导体衬底的表面的另一部分。 并且，在第二开口中形成第二半导体图案。

公开(公告)号：US20150022920A1

公开(公告)日：2015-01-22

申请号：US13943804

申请日：2013-07-17

Applicant: United Microelectronics Corporation

Inventor： Shao-Ping CHEN

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L29/785

Abstract: A chip with electrostatic discharge protection function includes two power rails, a pin, a P-type FinFET, an N-type FinFET, two Fin-resistors, two diodes and an ESD unit. The pin is electrically connected to one power rail sequentially through one Fin-resistor and the P-type FinFET and electrically connected to the other power rail sequentially through the other Fin-resistor and the N-type FinFET. The two FinFETs are configured to have the control terminals thereof for receiving a transmission signal. The pin is further electrically connected to the two power rails through the two diodes, respectively. The ESD unit, electrically connected between the first and second power rails, is configured to provide an ESD path between the first and second power rails.

Abstract translation: 具有静电放电保护功能的芯片包括两个电源轨，一个引脚，一个P型FinFET，一个N型FinFET，两个Fin电阻，两个二极管和一个ESD单元。 该引脚通过一个Fin电阻器和P型FinFET依次电连接到一个电源轨，并通过另一个Fin电阻器和N型FinFET电连接到另一个电源轨。 两个FinFET被配置为具有用于接收传输信号的控制端。 引脚分别通过两个二极管电连接到两个电源轨。 电连接在第一和第二电源轨之间的ESD单元被配置为在第一和第二电源轨之间提供ESD路径。

公开(公告)号：US08921185B2

公开(公告)日：2014-12-30

申请号：US14255948

申请日：2014-04-17

Applicant: United Microelectronics Corporation

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Ke-Chi Chen ,  Chih-Ming Wang ,  Chi-Cheng Huang

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/82345 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.

Abstract translation: 一种用于制造集成电路的方法包括以下步骤：提供具有形成在其中的至少一个隔离结构的衬底，以便将衬底分离成具有形成在其上的第一层叠结构的第一有源区和具有第二层的第二有源区 堆叠结构; 形成覆盖所述第一堆叠结构和所述第二堆叠结构的层间电介质层; 以及平坦化所述层间电介质层以露出所述第一堆叠结构的顶表面，其中所述第二堆叠结构在平坦化之后仍被所述层间介电层覆盖。

公开(公告)号：US20140377887A1

公开(公告)日：2014-12-25

申请号：US13921220

申请日：2013-06-19

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yi-Ching WU ,  Tzu-Hung Yang ,  Chih-Chung Wu

IPC: H01L21/306 ,  H01L21/66

CPC classification number: H01L21/30625 ,  B24B37/042 ,  B24B49/006 ,  H01L21/31053 ,  H01L22/12 ,  H01L22/26

Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.

Abstract translation: 一种用于平面化半导体器件的方法，其中所述方法包括以下步骤：在衬底上形成至少一个图案化金属层。 在图案化金属层和基板上设置具有第一区域和第二区域的材料层，其中在第一区域和第二区域之间存在台阶高度。 然后在材料层上执行具有用于将第一区域处的材料层去除第二区域的相对速度的第一选择比率的第一抛光工艺。 随后，在材料层上进行第二抛光工艺，该第二抛光工艺具有用于在第一区域去除材料层的相对速度的第二选择比，并且第二选择比大于第一选择比。

公开(公告)号：US08917109B2

公开(公告)日：2014-12-23

申请号：US13855708

申请日：2013-04-03

Applicant: United Microelectronics Corporation

Inventor： Shi-Wen Chen ,  Yung-Hsiang Lin

IPC: G01R31/02 ,  G01R31/26 ,  G01R29/02 ,  G01R31/28

CPC classification number: G01R29/023 ,  G01R31/2851 ,  G01R31/31725

Abstract: A pulse width estimation method, applied between an integrated circuit and a circuit system for generating a reference pulse with a predetermined pulse width, includes steps for the following: generating an under-test pulse with an under-test pulse width by the integrated circuit; delivering the under-test and reference pulses to the integrated circuit for multiplying the under-test pulse width and the predetermined pulse width thereof by a timing gain and thereby obtaining a gained under-test pulse and a gained reference pulse, respectively; providing, by the integrated circuit, a count pulse for sampling the gained under-test pulse and the gained reference pulse and thereby obtaining a first count number and a second count number, respectively; and estimating the under-test pulse width by using the predetermined pulse width, the first count number and the second count number. A pulse width estimation device is also provided.

Abstract translation: 应用于集成电路和用于产生具有预定脉冲宽度的参考脉冲的电路系统之间的脉冲宽度估计方法包括以下步骤：通过集成电路产生具有欠测脉冲宽度的欠测脉冲; 将未测试和参考脉冲传送到集成电路，以将欠测脉冲宽度和其预定脉冲宽度乘以定时增益，从而分别获得获得的未测试脉冲和获得的参考脉冲; 通过集成电路提供用于对所获得的被测试脉冲和所获得的参考脉冲进行采样的计数脉冲，从而分别获得第一计数数和第二计数数; 以及通过使用预定脉冲宽度，第一计数和第二计数来估计欠测脉冲宽度。 还提供了一种脉冲宽度估计装置。

公开(公告)号：US20140300385A1

公开(公告)日：2014-10-09

申请号：US13855708

申请日：2013-04-03

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Shi-Wen CHEN ,  Yung-Hsiang LIN

IPC: G01R29/02 ,  G01R31/28

CPC classification number: G01R29/023 ,  G01R31/2851 ,  G01R31/31725

Abstract: A pulse width estimation method, applied between an integrated circuit and a circuit system for generating a reference pulse with a predetermined pulse width, includes steps for the following: generating an under-test pulse with an under-test pulse width by the integrated circuit; delivering the under-test and reference pulses to the integrated circuit for multiplying the under-test pulse width and the predetermined pulse width thereof by a timing gain and thereby obtaining a gained under-test pulse and a gained reference pulse, respectively; providing, by the integrated circuit, a count pulse for sampling the gained under-test pulse and the gained reference pulse and thereby obtaining a first count number and a second count number, respectively; and estimating the under-test pulse width by using the predetermined pulse width, the first count number and the second count number. A pulse width estimation device is also provided.

Abstract translation: 应用于集成电路和用于产生具有预定脉冲宽度的参考脉冲的电路系统之间的脉冲宽度估计方法包括以下步骤：通过集成电路产生具有欠测脉冲宽度的欠测脉冲; 将未测试和参考脉冲传送到集成电路，以将欠测脉冲宽度和其预定脉冲宽度乘以定时增益，从而分别获得获得的未测试脉冲和获得的参考脉冲; 通过集成电路提供用于对所获得的被测试脉冲和所获得的参考脉冲进行采样的计数脉冲，从而分别获得第一计数数和第二计数数; 以及通过使用预定脉冲宽度，第一计数和第二计数来估计欠测脉冲宽度。 还提供了一种脉冲宽度估计装置。