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公开(公告)号：US20220011352A1
公开(公告)日：2022-01-13
申请号：US16923991
申请日：2020-07-08
Applicant: Apple Inc.
Inventor： Yashar Rajavi , Sohrab Emami-Neyestanak , Abbas Komijani
Abstract: A power detector circuit that rejects the common mode portion of a differential signal is disclosed. The circuit includes a differential input having first and second input nodes. Differential and common mode circuit paths are coupled to the differential input. The common mode circuit path includes first and second capacitors coupled to respective first terminals of first and second input nodes of the differential input. The second terminal of each of the first and second capacitors is coupled to a gate terminal of a first bias transistor. The common mode circuit path is configured to reject a common mode portion of a differential input signal provided to the differential input such that a differential output signal is indicative of an amount of power of a differential portion of the differential input signal.
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公开(公告)号：US20210358677A1
公开(公告)日：2021-11-18
申请号：US15930084
申请日：2020-05-12
Applicant: Apple Inc.
Inventor： Hongrui Wang , Saihua Lin , Abbas Komijani , Sohrab Emami-Neyestanak
Abstract: Radio frequency filtering circuitry blocks certain frequencies in an outgoing signal so that the signal may be transmitted over a desired frequency. The radio frequency filtering circuitry includes a first inductor having a first coil and a second inductor coupled to and disposed within the first coil. The second inductor has a second coil and a third coil symmetrical to the second coil. When current is applied to the radio frequency filtering circuitry, the current in the second coil causes a first induced current in the first coil and the current in the third coil causes a second induced current in the first coil, wherein the second induced current is approximately equal in magnitude and opposite in direction to the first induced current. As such, the second induced current may compensate for the first induced current.
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公开(公告)号：US10804847B2
公开(公告)日：2020-10-13
申请号：US16274193
申请日：2019-02-12
Applicant: Apple Inc.
Inventor： Abbas Komijani , Sohrab Emami-Neyestanak , Yashar Rajavi
Abstract: A voltage controlled oscillator (VCO) having a harmonic trap is disclosed. A VCO includes first and second transistors cross-coupled with one another. The VCO further includes a first inductor having first and second loops coupled to one another, wherein the first inductor is arranged such that current flow through first loop is in the opposite direction of current flow in the second loop. The VCO further includes a second inductor that implements a third loop surrounding the first inductor.
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公开(公告)号：US20200259455A1
公开(公告)日：2020-08-13
申请号：US16274193
申请日：2019-02-12
Applicant: Apple Inc.
Inventor： Abbas Komijani , Sohrab Emami-Neyestanak , Yashar Rajavi
IPC: H03B5/12
Abstract: A voltage controlled oscillator (VCO) having a harmonic trap is disclosed. A VCO includes first and second transistors cross-coupled with one another. The VCO further includes a first inductor having first and second loops coupled to one another, wherein the first inductor is arranged such that current flow through first loop is in the opposite direction of current flow in the second loop. The VCO further includes a second inductor that implements a third loop surrounding the first inductor.
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公开(公告)号：US20250105811A1
公开(公告)日：2025-03-27
申请号：US18662354
申请日：2024-05-13
Applicant: Apple Inc.
Inventor： Milad Darvishi , Hongrui Wang , Abbas Komijani
Abstract: Systems and methods are provided for using a metal oxide semiconductor based (MOS-based) resistor bank as a load of an amplifier/mixer to adjust the gain of the amplifier/mixer across PVT variations. The gain is adjusted by regulating the impedance of the MOS-based resistor bank to emulate a desirable resistance change over temperature across all PTV variations. The voltage adding on the gate of the MOS-based resistor bank is controlled so that the resistance of the MOS-based resistor bank is a desired value and follow a predetermined variation across the PVT variations.
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Patent Agency Ranking
公开(公告)号：US20250096836A1
公开(公告)日：2025-03-20
申请号：US18672960
申请日：2024-05-23
Applicant: Apple Inc.
Inventor： Nitesh Singhal , Mark G. Forbes , Abbas Komijani , Jong Seok Park , Youngchang Yoon , Georgios Palaskas
IPC: H04B1/40 , H03K17/687 , H03M1/66 , H04B17/21
Abstract: Wireless circuitry is provided that includes a radio-frequency circuit having an input transistor and bias point selection circuitry configured to determine an optimal bias voltage for the input transistor. The bias point selection circuitry may include a replica transistor, a voltage generator configured to output one or more voltage levels to a gate terminal of the replica transistor, a current-to-voltage converter coupled to a source-drain terminal of the replica transistor, an analog-to-digital converter configured to receive analog voltages from the current-to-voltage converter and to output corresponding digital codes based on the received analog voltages, and associated control circuitry configured to receive the digital codes from the analog-to-digital converter and to adjust the voltage generator to output the optimal bias voltage based on the digital codes. The optimal bias voltage produces a third order transconductance of zero for the input transistor, which results in improved linearity for the radio-frequency circuit.
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公开(公告)号：US12244329B2
公开(公告)日：2025-03-04
申请号：US18484265
申请日：2023-10-10
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Xinhua Chen
IPC: H04B1/04
Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.
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公开(公告)号：US20250039805A1
公开(公告)日：2025-01-30
申请号：US18358516
申请日：2023-07-25
Applicant: Apple Inc.
Inventor： Franz J Eder , Carlo Tosetti , Josef Hagn , Andre Janssen , Abbas Komijani , Iliah Konstantinovsky , Roman Rainov , Amit Freiman , Amitoj Singh , Bernhard Sogl
Abstract: A user equipment (UE) device may communicate with a wireless base station (BS). Each antenna in a phased antenna array on the UE may receive a reference signal transmitted by the BS during the beam training interval. Transceiver circuitry may measure wireless performance metric data from the reference signal. While receiving the reference signal, control circuitry may selectively activate different individual antennas, may selectively activate different subsets of antennas, or may concurrently activate all of the antennas in the array. The control circuitry may identify, based on the wireless performance metric data, a first set of the antennas in the array to that are being blocked by an external object and a second set of antennas array that are not blocked. After the beam training interval, the transceiver may use the second set of antennas to convey wireless data with the BS while the first set of antennas are disabled.
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公开(公告)号：US20250030445A1
公开(公告)日：2025-01-23
申请号：US18356956
申请日：2023-07-21
Applicant: Apple Inc.
Inventor： Tarek Khedr Abdalla Mealy , Abbas Komijani , Zhengan Yang , Reetika K Agarwal , Hongrui Wang , Zhang Jin
Abstract: This disclosure is directed to a power combiner/divider with improved operating frequency range (e.g., bandwidth) compared to other power combiners/dividers. The power combiner/divider may include an isolation circuit including a first resonant circuit and a second resonant circuit coupled to terminals (e.g., input terminals, output terminals) of the power combiner/divider. The first resonant circuit may attenuate signals having frequencies in a first frequency range below an attenuation threshold between the terminals of the power combiner/divider. The second resonant circuit may attenuate signals having frequencies in a second frequency range below an attenuation threshold between the terminals of the power combiner/divider. Accordingly, the isolation circuit may improve isolation between multiple terminals of the power combiner/divider at a wider bandwidth compared to other power combiners/dividers based attenuating cross-talk between the terminal at the first frequency range and the second frequency range.
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公开(公告)号：US20240429962A1
公开(公告)日：2024-12-26
申请号：US18214307
申请日：2023-06-26
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Ali Parsa
Abstract: In some source degeneration-based cascode LNAs, a cascode transistor may contribute a large portion of noise at mmWave frequencies due to lower output impedance from a bottom transistor (e.g., amplifying transistor or transconductance transistor) of the cascode. The cascode noise may negatively impact performance of the LNA. A first inductor (e.g., cascode inductor) may be coupled to the source of the cascode transistor and a second inductor (e.g., notch inductor) may be coupled to the gate of the bottom transistor such that the cascode inductor and a notch inductor inductively couple to each other, introducing a reverse-transmission zero in-band to reduce or eliminate cascode noise contribution and neutralize gate-drain capacitance of the bottom transistor with minimal area consumption.
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