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    Always-On Audio Control for Mobile Device
    31.
    发明申请
    Always-On Audio Control for Mobile Device 审中-公开

    公开(公告)号：US20190287532A1

    公开(公告)日：2019-09-19

    申请号：US16397057

    申请日：2019-04-29

    Applicant: Apple Inc.

    Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

    IPC: G10L15/28 ,  G06F1/3287 ,  G06F1/3228 ,  G06F3/16 ,  G10L15/22 ,  G06F1/32

    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

    Video encoder with context switching
    32.
    发明授权
    Video encoder with context switching 有权

    公开(公告)号：US10313683B2

    公开(公告)日：2019-06-04

    申请号：US14474114

    申请日：2014-08-30

    Applicant: Apple Inc.

    Inventor： Joseph J. Cheng ,  Timothy J. Millet ,  Shun Wai Go ,  Guy Cote

    IPC: H04N19/172 ,  H04N19/176 ,  H04N19/46 ,  G06F9/46 ,  G06F9/48 ,  H04N19/129 ,  H04N19/127 ,  H04N19/174 ,  H04N19/42 ,  H04N19/40 ,  H04N19/182

    Abstract: A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

    Parameter FIFO
    35.
    发明授权
    Parameter FIFO 有权
    参数FIFO

    公开(公告)号：US09262798B2

    公开(公告)日：2016-02-16

    申请号：US14263424

    申请日：2014-04-28

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet

    IPC: G09G5/39 ,  G06T1/60 ,  G09G5/36 ,  G09G5/14

    CPC classification number: G06T1/60 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/10 ,  G09G2360/12 ,  G09G2360/127

    Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

    Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。

    Network display support in an integrated circuit
    37.
    发明授权
    Network display support in an integrated circuit 有权
    集成电路中的网络显示支持

    公开(公告)号：US09087393B2

    公开(公告)日：2015-07-21

    申请号：US13788209

    申请日：2013-03-07

    Applicant: Apple Inc.

    Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Timothy J. Millet

    IPC: G09G5/39 ,  G06T1/60

    CPC classification number: G06T1/60 ,  G09G5/006 ,  G09G2340/0442 ,  G09G2340/0492 ,  G09G2360/125 ,  G09G2370/10

    Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.

    Abstract translation: 在一个实施例中，系统包括针对与网络显示器进行通信而优化的硬件。 硬件可以包括显示管单元，其被配置为将来自视频序列的一个或多个静态图像和一个或多个帧组合以形成用于由网络显示器显示的帧。 显示管单元可以包括写回单元，其被配置为将复合帧写回到存储器，可以使用视频编码器硬件来选择性地对帧进行编码，并将其分组化以便通过网络传输到网络显示器。 在一个实施例中，显示管单元可以被配置为在帧的生成期间向视频编码器发出中断，以重叠编码和帧生成。

    Combined Transparent/Non-Transparent Cache
    38.
    发明申请
    Combined Transparent/Non-Transparent Cache 审中-公开
    组合透明/不透明缓存

    公开(公告)号：US20150149734A1

    公开(公告)日：2015-05-28

    申请号：US14611423

    申请日：2015-02-02

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F12/08

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

    Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。

    Buffer Underrun Handling
    39.
    发明申请
    Buffer Underrun Handling 审中-公开
    缓冲区欠载处理

    公开(公告)号：US20140139535A1

    公开(公告)日：2014-05-22

    申请号：US14163326

    申请日：2014-01-24

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet ,  Brijesh Tripathi

    IPC: G06T1/60

    CPC classification number: G06T1/60 ,  G09G5/39

    Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

    Abstract translation: 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

    Hardware automatic performance state transitions in system on processor sleep and wake events
    40.
    发明授权
    Hardware automatic performance state transitions in system on processor sleep and wake events 有权
    系统中处理器睡眠和唤醒事件的硬件自动性能状态转换

    公开(公告)号：US08656196B2

    公开(公告)日：2014-02-18

    申请号：US13863554

    申请日：2013-04-16

    Applicant: Apple Inc.

    Inventor： Josh P. de Cesare ,  Jung Wook Cho ,  Toshinari Takayanagi ,  Timothy J. Millet

    IPC: G06F1/00 ,  G06F1/26 ,  G09G3/18 ,  G11C5/14 ,  H04M1/00

    CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

    Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

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