公开(公告)号：US20130240996A1

公开(公告)日：2013-09-19

申请号：US13520611

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately.

Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域 所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层 ，第二功函数金属扩散阻挡层和栅极填充层，功函数接近价带（导带）边; 每个第二栅极堆叠结构包括第二栅极绝缘层，改性的第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，所述第二功函数金属层包括植入功函数调节 掺杂离子，其同时扩散到下面的第一功函数层以调节阈值，使得栅极的功函数接近价带（导带）边缘并与原始第一功函数相反，从而调节 工作功能准确。

公开(公告)号：US20130228893A1

公开(公告)日：2013-09-05

申请号：US13145301

申请日：2011-04-22

Applicant: Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

Inventor： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC: H01L21/762 ,  H01L29/02

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L29/02

Abstract: A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.

Abstract translation: 提供了沟槽隔离结构及其形成方法。 沟槽隔离结构包括：半导体衬底和形成在半导体衬底的表面上并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。 通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

公开(公告)号：US20130105859A1

公开(公告)日：2013-05-02

申请号：US13582432

申请日：2011-11-28

Applicant: Guilei Wang ,  Chunlong Li ,  Chao Zhao

Inventor： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/28264 ,  H01L21/823807 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/51 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，形成在衬底上的绝缘隔离层，形成在绝缘隔离层中的第一有源区和第二有源区，其特征在于，第一有源区 区域层和/或第二有源区层比衬底高。 根据本发明的半导体器件及其制造方法，使用由与衬底不同的材料形成的有源区，增加沟道区中的载流子迁移率，从而显着改善器件响应速度 设备性能大大提升。 此外，与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US20130061884A1

公开(公告)日：2013-03-14

申请号：US13641874

申请日：2012-03-23

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC: B08B3/04

CPC classification number: H01L21/67051

Abstract: A method for cleaning wafer after chemical mechanical planarization that includes placing the wafer in the wafer holder and rotating the wafer holder and the wafer simultaneously, cleaning with chemicals by providing the wafer surface with chemical detergent through the detergent supply cantilever that keeps a certain distance away from the wafer surface, cleaning with deionized water by providing the wafer surface with deionized water through the detergent supply cantilever to remove the chemical detergent and cleaning products. The method also includes the second clean for better cleaning effect and drying the wafer out. According to the wafer cleaning method, the non-contact detergent and deionized water supply cantilever used for wafer cleaning reduces or eliminates the possible problems in making macro scratches on wafer surface in the scrubbing process and increases the yield for wafer devices.

Abstract translation: 一种用于在化学机械平面化之后清洁晶片的方法，包括将晶片放置在晶片保持器中并同时旋转晶片保持器和晶片，用化学药剂清洗通过在一定距离之外的洗涤剂供给悬臂的化学清洁剂 从晶片表面，用去离子水清洗，通过提供晶片表面的去离子水通过洗涤剂供应悬臂来去除化学清洁剂和清洁产品。 该方法还包括第二次清洁以获得更好的清洁效果并干燥晶片。 根据晶片清洗方法，用于晶片清洗的非接触式洗涤剂和去离子水供应悬臂减少或消除了在洗涤过程中在晶片表面上产生宏观划痕的可能问题，并提高了晶片装置的产量。

公开(公告)号：US20130059434A1

公开(公告)日：2013-03-07

申请号：US13509722

申请日：2011-11-29

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Xiaobin He ,  Yihong Lu

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Xiaobin He ,  Yihong Lu

IPC: H01L21/28

CPC classification number: H01L29/66606 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process. Such a design has the advantages of simplifying complexity of process integration on one hand and greatly strengthening control of defects by CMP process on the other hand, thereby avoiding the defects like erosion and dishing that may be produced between different metal materials.

Abstract translation: 本发明提供了一种用于在栅极最后工艺中同时制造栅电极和接触导线的方法，包括以下步骤：在衬底上的层间电介质层中形成栅极沟槽; 在栅极沟槽和层间电介质层上形成填充层; 蚀刻填充层和层间电介质层以暴露衬底，从而形成源极/漏极接触孔; 去除填充层以暴露栅极沟槽和源极/漏极接触孔; 在源极/漏极接触孔中形成金属硅化物; 在栅极沟槽中沉积栅极电介质层和金属栅极; 在栅极沟槽和源极/漏极接触孔中填充金属; 并平坦化填充的金属。 根据本发明的制造方法，栅极电极线将由与接触孔相同的金属材料制成，使得两者可以通过一个CMP工艺制造。 这样的设计一方面简化了工艺集成的复杂性，另一方面通过CMP工艺大大加强了缺陷的控制，从而避免了不同金属材料之间可能产生的侵蚀和凹陷等缺陷。

公开(公告)号：US20130037859A1

公开(公告)日：2013-02-14

申请号：US13321852

申请日：2011-08-12

Applicant: Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

Inventor： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

IPC: H01L27/10 ,  H01L21/326 ,  H01L23/522 ,  H01L29/788 ,  H01L29/92 ,  H01L23/525

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.

Abstract translation: 提供了半导体器件及其编程方法。 半导体器件包括：其中形成有互连的半导体衬底; 穿透半导体衬底的透硅通孔（TSV）; 以及可以在导通和关断状态之间切换的可编程器件，TSV通过可编程器件连接到互连。 本发明有利于提高TSV应用的灵活性。

公开(公告)号：US20120273886A1

公开(公告)日：2012-11-01

申请号：US13380828

申请日：2011-08-12

Applicant: Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

Inventor： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

Abstract translation: 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

公开(公告)号：US20120190188A1

公开(公告)日：2012-07-26

申请号：US13379967

申请日：2011-02-28

Applicant: Chao Zhao ,  Wenwu Wang ,  Huicai Zhong

Inventor： Chao Zhao ,  Wenwu Wang ,  Huicai Zhong

IPC: H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a gap includes: providing a semiconductor substrate, at least having an metal interconnect layer and an insulating dielectric layer on top of the underlying metal interconnect layer, the insulating dielectric layer having a gap; forming a diffusion bather layer and a seed layer sequentially in the gap and on a surface of the insulating dielectric layer outside the gap; forming a mask layer on a surface of the seed layer outside of the gap; and depositing a metal layer on the semiconductor substrate with the mask layer, the metal layer filling the gap.

Abstract translation: 用于填充间隙的方法包括：提供至少在下面的金属互连层的顶部上具有金属互连层和绝缘介电层的半导体衬底，绝缘介电层具有间隙; 在所述间隙中的间隙和所述绝缘介电层的表面上顺序地形成扩散洗礼层和种子层; 在所述间隙的外侧的种子层的表面上形成掩模层; 以及用所述掩模层在所述半导体衬底上沉积金属层，所述金属层填充所述间隙。

公开(公告)号：US20120181586A1

公开(公告)日：2012-07-19

申请号：US13379120

申请日：2011-04-22

Applicant: Jun Luo ,  Chao Zhao

Inventor： Jun Luo ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/66643 ,  H01L29/7839

Abstract: The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.

Abstract translation: 本发明公开了一种通过门最后工艺制造的新型MOSFET器件及其实现方法，该器件包括：衬底; 栅极叠层结构位于衬底的沟道区上，其任一侧消除了传统隔离间隔物; 构成源极/漏极区域的外延生长的超薄金属硅化物。 其中该器件消除了传统隔离间隔物下面的高电阻区域; 在源极/漏极和沟道区之间形成具有经过离子注入的掺杂剂偏析区域，这降低了金属硅化物源极/漏极与沟道之间的肖特基势垒高度。 同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。 根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

公开(公告)号：US20120156873A1

公开(公告)日：2012-06-21

申请号：US13063922

申请日：2011-01-27

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong

IPC: H01L21/28

CPC classification number: H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.

Abstract translation: 一种用于限制金属硅化物向通道区域的横向侵入的方法，包括：提供半导体衬底，形成在半导体衬底上的栅堆叠，形成在栅叠层一侧的半导体中的源区， 漏极区域形成在栅极堆叠的另一侧上的半导体衬底中; 在所述栅极堆叠和所述半导体衬底上形成牺牲隔离物; 沉积用于覆盖半导体衬底，栅极堆叠和牺牲隔离物的金属层; 对所述半导体基板进行热处理，由此使所述金属层与所述源极区域和所述漏极区域中的所述牺牲隔离物和所述半导体基板反应; 去除牺牲间隔物，牺牲间隔物和金属层的反应产物，以及不与牺牲间隔物反应的金属层的一部分。