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    Hardware and software methodologies for detecting illegal memory address of a memory access operation
    32.
    发明授权
    Hardware and software methodologies for detecting illegal memory address of a memory access operation 有权
    用于检测内存访问操作的非法内存地址的硬件和软件方法

    公开(公告)号：US09535613B2

    公开(公告)日：2017-01-03

    申请号：US14551915

    申请日：2014-11-24

    Applicant: Futurewei Technologies, Inc.

    Inventor： Reza Yazdani ,  Chen Tian

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0614 ,  G06F3/0653 ,  G06F3/0673 ,  G06F8/00 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3861 ,  G06F12/0292 ,  G06F12/1441 ,  G06F21/00 ,  G06F21/53

    Abstract: A system for providing bound checking to insure memory accessed, including indirect object access through pointers, is within a range of defined object bounds is disclosed herein. Embodiments of the present disclosure provide hardware and software methodology for bound checking, where bound checking is performed in hardware and in parallel with the execution of the memory accesses using dedicated hardware. There is reduced overhead associated with the enforcement of bound checking, and hardware is modified to include new registers and/or instructions for bound checking support. An exception is raised when an out of bound violation is detected. According to some embodiments, a compiler extracts bound information from the respective programming language (e.g. C/C++, Java) and generates tables with special APIs known to the hardware that enables both execution of the program and bound checking to be performed simultaneously.

    Abstract translation: 本文公开了一种用于提供绑定检查以确保所访问的存储器（包括通过指针的间接对象访问）的系统在限定的对象边界的范围内。 本公开的实施例提供用于绑定检查的硬件和软件方法，其中绑定检查在硬件中执行并且与使用专用硬件的存储器访问的执行并行。 与执行绑定检查相关联的开销减少，并且修改硬件以包括用于绑定检查支持的新的寄存器和/或指令。 当检测到超出限制的违规时会引发异常。 根据一些实施例，编译器从相应的编程语言（例如C / C ++，Java）中提取绑定信息，并生成具有硬件已知的特殊API的表，其使得能够同时执行程序的执行和绑定检查。

    Optimizing Synchronous Write via Speculation
    33.
    发明申请
    Optimizing Synchronous Write via Speculation 有权
    通过投机优化同步写入

    公开(公告)号：US20160216905A1

    公开(公告)日：2016-07-28

    申请号：US14606803

    申请日：2015-01-27

    Applicant: Futurewei Technologies, Inc.

    Inventor： Reza Yazdani ,  Chen Tian

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0671 ,  G06F3/0685

    Abstract: A method implemented in a data processing system comprising receiving an input/output (IO) write request from a processing thread to transfer data from a memory of the data processing system to an IO device, setting the memory as read-only memory to protect the data from overwrite before the data is transferred to the IO device, and sending, in response to the IO write request, a speculative IO write completion response to the processing thread to enable the processing thread to continue execution without waiting for the data to be transferred to the IO device.

    Abstract translation: 一种在数据处理系统中实现的方法，包括从处理线程接收输入/输出（IO）写入请求，以将数据从数据处理系统的存储器传送到IO设备，将存储器设置为只读存储器，以保护 在将数据传送到IO设备之前，覆盖的数据被重写，并且响应于IO写入请求，发送对处理线程的推测性IO写入完成响应，以使得处理线程能够继续执行而不等待数据被传送 到IO设备。

    System and Method for Isolating I/O Execution via Compiler and OS Support
    34.
    发明申请
    System and Method for Isolating I/O Execution via Compiler and OS Support 有权
    通过编译器和操作系统支持隔离I / O执行的系统和方法

    公开(公告)号：US20150234640A1

    公开(公告)日：2015-08-20

    申请号：US14184297

    申请日：2014-02-19

    Applicant: FutureWei Technologies, Inc.

    Inventor： Chen Tian ,  Handong Ye ,  Ziang Hu

    IPC: G06F9/45 ,  G06F13/24

    CPC classification number: G06F9/4881 ,  G06F8/41 ,  G06F8/423 ,  G06F8/451 ,  G06F8/48 ,  G06F8/51 ,  G06F9/4812 ,  G06F13/24

    Abstract: Embodiments are provided for isolating Input/Output (I/O) execution by combining compiler and Operating System (OS) techniques. The embodiments include dedicating selected cores, in multicore or many-core processors, as I/O execution cores, and applying compiler-based analysis to classify I/O regions of program source codes so that the OS can schedule such regions onto the designated I/O cores. During the compilation of a program source code, each I/O operation region of the program source code is identified. During the execution of the compiled program source code, each I/O operation region is scheduled for execution on a preselected I/O core. The other regions of the compiled program source code are scheduled for execution on other cores.

    Abstract translation: 提供了通过组合编译器和操作系统（OS）技术来隔离输入/输出（I / O）执行的实施例。 这些实施例包括将多核或多核处理器中的所选核心专用于I / O执行核心，以及应用基于编译器的分析来对程序源代码的I / O区域进行分类，以便OS可以将这些区域调度到指定的I / O核心。 在编译程序源代码期间，识别程序源代码的每个I / O操作区域。 在执行编译的程序源代码期间，每个I / O操作区域被调度为在预选的I / O核心上执行。 编译的程序源代码的其他区域被安排在其他核心上执行。

    Model checker for finding distributed concurrency bugs
    36.
    发明授权
    Model checker for finding distributed concurrency bugs 有权

    公开(公告)号：US10599552B2

    公开(公告)日：2020-03-24

    申请号：US15962873

    申请日：2018-04-25

    Applicant: Futurewei Technologies, Inc. ,  University of Chicago

    Inventor： Jeffrey Lukman ,  Huan Ke ,  Haryadi Gunawi ,  Feng Ye ,  Chen Tian ,  Shen Chi Chen

    IPC: G06F11/36

    Abstract: Described herein are systems and methods for distributed concurrency (DC) bug detection. The method includes identifying a plurality of nodes in a distributed computing cluster; identifying a plurality of messages to be transmitted during execution of an application by the distributed computing cluster; determining a set of orderings of the plurality of messages for DC bug detection, the set of orderings determined based upon the plurality of nodes and the plurality of messages; removing a subset of the orderings from the set of orderings based upon one or more of a state symmetry algorithm, a disjoint-update independence algorithm, or a zero-crash-impact reordering algorithm; and performing DC bug detection testing using the set of orderings after the subset of the orderings is removed from the set of orderings.

    PROXY APPARATUS AND METHOD FOR DATA COLLECTION
    39.
    发明申请
    PROXY APPARATUS AND METHOD FOR DATA COLLECTION 审中-公开

    公开(公告)号：US20180302486A1

    公开(公告)日：2018-10-18

    申请号：US15486151

    申请日：2017-04-12

    Applicant: Futurewei Technologies, Inc.

    Inventor： Lin Ma ,  Peter M. Pham ,  Wei Chung Chuo ,  Feng Ye ,  Lawrence Davison ,  Chen Tian

    IPC: H04L29/08 ,  H04L12/26

    Abstract: A proxy processing device and associated method are provided to receive control signals from a manager that are based on user input received by the manager. Further, the control signals are sent to an agent for controlling one or more aspects of a collection of data from at least one node and a communication of the data to a destination via at least one channel. The collection of the data and the communication of the data is performed by the agent utilizing a plurality of software components that each customizes the one or more aspects of the collection of the data and the communication of the data.

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