公开(公告)号：US20160379873A1

公开(公告)日：2016-12-29

申请号：US14750741

申请日：2015-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract translation: 用于填充结构之间的间隙的方法包括通过间隙形成彼此相邻的多个高纵横比结构，在结构的顶部上形成第一介电层，并在结构上共形沉积间隔电介质层。 间隔电介质层从水平表面去除，保护层共形沉积在结构上。 间隙填充有可流动电介质，其通过选择性蚀刻工艺凹陷到结构侧壁的高度，使得保护层保护结构侧壁上的间隔电介质层。 使用比保护层更高的蚀刻电阻将第一介电层和间隔电介质层暴露在高度之上，以通过蚀刻工艺保持间隔层电介质的尺寸。 间隙由高密度等离子体填充物填充。

公开(公告)号：US10957544B2

公开(公告)日：2021-03-23

申请号：US15484173

申请日：2017-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie

IPC: H01L21/283 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L27/02 ,  H01L21/033 ,  H01L21/3105

Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

公开(公告)号：US10797154B2

公开(公告)日：2020-10-06

申请号：US15190778

申请日：2016-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/283 ,  H01L27/088 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US10186599B1

公开(公告)日：2019-01-22

申请号：US15655547

申请日：2017-07-20

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chen Fan ,  Andrew M. Greene ,  Sean Lian ,  Balasubramanian Pranatharthiharan ,  Mark V. Raymond ,  Ruilong Xie

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L29/51

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：US10002792B2

公开(公告)日：2018-06-19

申请号：US15624156

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US20170287785A1

公开(公告)日：2017-10-05

申请号：US15624156

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US09773885B2

公开(公告)日：2017-09-26

申请号：US15471733

申请日：2017-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US20170125543A1

公开(公告)日：2017-05-04

申请号：US14928719

申请日：2015-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US20170062325A1

公开(公告)日：2017-03-02

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V.V.S. Surisetty ,  Ruilong Xie

IPC: H01L23/528 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

Abstract translation: 自对准互连结构包括在衬底中图案化的翅片结构; 设置在所述鳍结构上的外延触点; 第一金属栅极和第二金属栅极，其设置在外延接触面上并基本上垂直于外延接触，第一金属栅极和第二金属栅极基本上彼此平行; 以及在第一和第二金属栅极之间的区域中与基板接触并与之接触的金属接触。

公开(公告)号：US09576954B1

公开(公告)日：2017-02-21

申请号：US14862258

申请日：2015-09-23

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Sanjay C. Mehta ,  Balasubramanian S. Pranatharthiharan ,  Ruilong Xie

IPC: H01L27/092 ,  H01L29/772 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76205 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

Abstract translation: 在栅极之间填充沟槽的方法包括在衬底上形成第一和第二虚拟栅极，第一和第二伪栅极包括牺牲栅极材料和硬掩模层; 沿着第一伪栅极的侧壁形成第一栅极间隔物，沿着第二虚拟栅极的侧壁形成第二栅极间隔物; 执行外延生长工艺以在第一和第二虚拟栅极之间的衬底上形成源极/漏极; 在第一和第二伪栅极和源极/漏极上设置保形衬垫; 在第一和第二伪栅极之间的保形衬垫上设置氧化物; 将氧化物凹陷到低于第一和第二伪栅极的硬掩模层的水平以形成凹陷氧化物; 以及在第一伪栅极和第二虚拟栅极之间的凹陷氧化物上沉积间隔物材料。