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    Integrated multiple gate length semiconductor device including self-aligned contacts
    35.
    发明授权
    Integrated multiple gate length semiconductor device including self-aligned contacts 有权
    集成多栅长半导体器件包括自对准触点

    公开(公告)号：US09466680B2

    公开(公告)日：2016-10-11

    申请号：US14825375

    申请日：2015-08-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Su Chen Fan ,  Balasubramanian Pranatharthiharan ,  Rajasekhar Venigalla

    IPC: H01L29/423 ,  H01L27/092 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/321 ,  H01L21/3213

    CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/1033 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/78

    Abstract: A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length and the second gate channel has a second length greater than the first length. A gate dielectric layer is formed in the first and second gate channels. A first plurality of work function metal layers is formed on the gate dielectric layer of the first gate channel. A second plurality of work function metal layers is formed on the gate dielectric layer of the second gate channel. A barrier layer is formed on each of the first and second plurality of work function metal layers, and the gate dielectric layer. The multi-channel semiconductor device further includes metal gate stacks formed on of the barrier layer such that the barrier layer is interposed between the metal gate stacks and the gate dielectric layer.

    Abstract translation: 多沟道半导体器件包括形成在半导体衬底中的第一和第二栅极沟道。 第一栅极沟道具有第一长度，并且第二栅极沟道具有大于第一长度的第二长度。 在第一和第二栅极通道中形成栅极电介质层。 在第一栅极沟道的栅介质层上形成第一多个功函数金属层。 在第二栅极沟道的栅极介电层上形成第二多个功函数金属层。 在第一和第二多个功函数金属层和栅介质层中的每一个上形成阻挡层。 多沟道半导体器件还包括形成在阻挡层上的金属栅极堆叠，使得阻挡层插入在金属栅极堆叠和栅极电介质层之间。

    Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods
    36.
    发明授权
    Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods 有权
    具有自对准接触工艺流程和制造方法中线路电容降低的集成电路

    公开(公告)号：US09443944B2

    公开(公告)日：2016-09-13

    申请号：US14541754

    申请日：2014-11-14

    Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hui Zang ,  Balasubramanian Pranatharthiharan

    IPC: H01L29/417 ,  H01L29/40 ,  H01L21/28

    CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76801 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/401 ,  H01L29/785

    Abstract: Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region.

    Abstract translation: 提供了用于形成具有自对准接触工艺流程和制造中线路电容减小的半导体器件的器件和方法。 一种方法包括例如：获得具有至少一个源极，漏极和栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 以及在所述第一和第二接触区域上形成至少一个第一和第二小接触。 一个中间半导体器件包括例如：具有栅极，源极区和漏极区的晶片; 位于所述源的一部分上方的至少一个第一接触区域; 至少一个第二接触区域位于所述排水管的一部分上方; 位于所述第一接触区域上方的至少一个第一小接触件; 以及位于第二接触区域上方的至少一个第二小接触件。

    CONTACT FORMATION FOR ULTRA-SCALED DEVICES
    37.
    发明申请
    CONTACT FORMATION FOR ULTRA-SCALED DEVICES 有权
    超声波设备的接触形式

    公开(公告)号：US20140339629A1

    公开(公告)日：2014-11-20

    申请号：US13894513

    申请日：2013-05-15

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Shom Ponoth ,  David V. Horak ,  Balasubramanian Pranatharthiharan

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7827 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66666

    Abstract: Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

    Abstract translation: 本发明的实施例提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地，半导体器件包括形成在衬底上的栅极晶体管，形成在沟槽硅化物（TS）层上并且邻近栅极晶体管定位的S / D接触，以及形成在栅极晶体管上的栅极接触，其中至少一个 栅极触点的一部分在TS层上对齐。 这种结构使得能够与TS层接触，从而减小栅极接触和源极/漏极之间的距离，这对于超区域缩放是期望的。

    Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
    38.
    发明授权
    Methods of forming a semiconductor device with a protected gate cap layer and the resulting device 有权
    用保护的栅极盖层形成半导体器件的方法和所得到的器件

    公开(公告)号：US08871582B2

    公开(公告)日：2014-10-28

    申请号：US13839626

    申请日：2013-03-15

    Applicant: GlobalFoundries Inc. ,  International Business Machines Corporation

    Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L29/4232 ,  H01L21/28247 ,  H01L29/66545 ,  H01L29/78

    Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

    Abstract translation: 一种方法包括形成凹入的栅极/间隔结构，其部分地限定间隔物/栅极盖凹部，在间隔物/栅极盖凹部中形成栅极盖层，在栅极盖层的上表面上形成栅极盖保护层，以及 去除栅极帽保护层的部分，留下栅极盖保护层的一部分位于栅极盖层的上表面上。 本文公开的装置包括定位在绝缘材料层中的栅极/间隔结构，位于栅极/间隔物结构上的栅极盖层，其中栅极盖层的侧壁接触绝缘材料层，栅极盖保护层 定位在栅极盖层的上表面上，其中栅极盖保护层的侧壁也接触绝缘材料层。

    METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
    39.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE 有权
    形成具有保护盖板层和结构设备的半导体器件的方法

    公开(公告)号：US20140264487A1

    公开(公告)日：2014-09-18

    申请号：US13839802

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

    Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

    Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

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