公开(公告)号：US09711447B1

公开(公告)日：2017-07-18

申请号：US15290277

申请日：2016-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Qiang Fang ,  Daniel W. Fisher ,  Haigou Huang ,  Jinping Liu ,  Haifeng Sheng ,  Zhiguo Sun

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/53238

Abstract: Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

公开(公告)号：US09275898B1

公开(公告)日：2016-03-01

申请号：US14637442

申请日：2015-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Zhiguo Sun ,  Yang Bum Lee ,  Huang Liu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53228 ,  C23C16/04 ,  C23C16/16 ,  C23C16/45523 ,  H01L21/28562 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76862 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a Co cap on a Cu interconnect in or through an ULK ILD with improved selectivity while protecting an ULK ILD surface are provided. Embodiments include providing a Cu filled via in an ULK ILD; depositing a Co precursor and H2 over the Cu-filled via and the ULK ILD, the Co precursor and H2 forming a Co cap over the Cu-filled via; depositing an UV cured methyl over the Co cap and the ULK ILD; performing an NH3 plasma treatment after depositing the UV cured methyl; and repeating the steps of depositing a Co precursor through performing an NH3 plasma treatment to remove impurities from the Co cap.

Abstract translation: 提供了在保护ULK ILD表面的情况下，通过ULK ILD或通过ULK ILD在Cu互连上形成Co帽的方法，其具有改进的选择性。 实施例包括在ULK ILD中提供Cu填充的通孔; 在Cu填充的通孔和ULK ILD上沉积Co前体和H 2，Co前体和H 2在Cu填充的通孔上形成Co盖; 在Co盖和ULK ILD上沉积UV固化的甲基; 沉积UV固化甲基后进行NH3等离子体处理; 并且重复以下步骤：通过进行NH 3等离子体处理来沉积Co前体以从Co盖去除杂质。

公开(公告)号：US10937685B2

公开(公告)日：2021-03-02

申请号：US16446588

申请日：2019-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Haiting Wang ,  Jiehui Shu

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.

公开(公告)号：US20210050419A1

公开(公告)日：2021-02-18

申请号：US16541600

申请日：2019-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US10896853B2

公开(公告)日：2021-01-19

申请号：US16396775

申请日：2019-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Rinus Tek Po Lee ,  Wei Hong ,  Hui Zang ,  Hong Yu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages. The present disclosure further provides a method of forming structures in a semiconductor device by forming a first and second cavities having sidewalls and bottom surfaces in a dielectric structure, where the first cavity has a narrower opening than the second cavity, forming a first material layer in the first and second cavities, forming a protective layer over the first material layer, where the protective layer fills the first cavity and conformally covers the sidewall and the bottom surfaces of the second cavity, performing a first isotropic etch on the protective layer to selectively remove a portion of the protective layer and form a retained portion of the protective layer, performing a second isotropic etch on the first material layer to selectively remove a portion of the first material layer and form a retained portion of the first material layer, removing the retained portion of the protective layer, and forming a second material layer in the first and second cavities, the second material layer being formed on the retained portion of the first material layer.

公开(公告)号：US10797046B1

公开(公告)日：2020-10-06

申请号：US16369788

申请日：2019-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L27/07 ,  H01L49/02 ,  H01L29/78 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L27/02 ,  H01L27/06

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material.

公开(公告)号：US20200303261A1

公开(公告)日：2020-09-24

申请号：US16360183

申请日：2019-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Jiehui Shu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.

公开(公告)号：US20200118927A1

公开(公告)日：2020-04-16

申请号：US16161590

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Guoxiang Ning ,  Jiehui Shu

IPC: H01L23/525 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.

公开(公告)号：US10522538B1

公开(公告)日：2019-12-31

申请号：US16032108

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

公开(公告)号：US20190355615A1

公开(公告)日：2019-11-21

申请号：US16525601

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.