公开(公告)号：US20080067660A1

公开(公告)日：2008-03-20

申请号：US11855958

申请日：2007-09-14

Applicant: Hye-Jin Kim ,  Kyung-Man Kim

Inventor： Hye-Jin Kim ,  Kyung-Man Kim

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: A semiconductor device package includes a semiconductor chip having bonding pads; a printed circuit board (PCB) including an insulation pattern with a groove and bonding electrodes corresponding to the bonding pads, the groove corresponding to the edge of the semiconductor chip and being formed to partially expose a lower portion of the edge of the semiconductor chip; an adhesive material provided for adhering the bottom of the semiconductor chip to the insulation pattern to mount the semiconductor chip on the PCB; bonding wires provided for electrically connecting the bonding electrodes to the corresponding bonding pads; and a molding material provided for sealing the PCB, the semiconductor chip, the adhesive material, and the bonding wires.

Abstract translation: 半导体器件封装包括具有接合焊盘的半导体芯片; 包括具有凹槽的绝缘图案和与所述接合焊盘对应的接合电极的印刷电路板（PCB），所述凹槽对应于所述半导体芯片的边缘并形成为部分地暴露所述半导体芯片的边缘的下部; 提供用于将半导体芯片的底部粘附到绝缘图案以将半导体芯片安装在PCB上的粘合材料; 用于将接合电极电连接到相应的接合焊盘的接合线; 以及用于密封PCB，半导体芯片，粘合材料和接合线的成型材料。

公开(公告)号：US20070236987A1

公开(公告)日：2007-10-11

申请号：US11727711

申请日：2007-03-28

Applicant: Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

Inventor： Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

公开(公告)号：US20070008769A1

公开(公告)日：2007-01-11

申请号：US11301322

申请日：2005-12-12

Applicant: Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

Inventor： Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Disclosed is a phase-changeable memory device and method of programming the same. The phase-changeable memory device includes memory cells each having multiple states, and a program pulse generator providing current pulses to the memory cells. The program pulse generator initializes a memory cell to a reset or set state by applying a first pulse thereto and thereafter provides a second pulse to program the memory cell to one of the multiple states. According to the invention, as a memory cell is programmed after being initialized to a reset or set state, it is possible to correctly program the memory cell without influence from the previous state of the memory cell.

Abstract translation: 公开了一种可变相存储器件及其编程方法。 相位可变存储器件包括各自具有多个状态的存储单元，以及向存储单元提供电流脉冲的编程脉冲发生器。 程序脉冲发生器通过向其施加第一个脉冲而将存储单元初始化为复位或置位状态，此后提供第二脉冲以将存储器单元编程为多个状态之一。 根据本发明，由于在初始化为复位或置位状态之后对存储单元进行编程，所以可以在不影响存储单元的先前状态的情况下正确编程存储单元。

公开(公告)号：US08643193B2

公开(公告)日：2014-02-04

申请号：US13630619

申请日：2012-09-28

Applicant: Hye-Jin Kim ,  Byung-Seo Kim ,  Sunpil Youn

Inventor： Hye-Jin Kim ,  Byung-Seo Kim ,  Sunpil Youn

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/4911 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

公开(公告)号：US20130265837A1

公开(公告)日：2013-10-10

申请号：US13710504

申请日：2012-12-11

Applicant: Yong Jin Kwon ,  Kwang Jin Lee ,  Hye-Jin Kim

Inventor： Yong Jin Kwon ,  Kwang Jin Lee ,  Hye-Jin Kim

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0088

Abstract: A non-volatile memory device includes a set pulse generator configured to generate a set pulse, a reset pulse generator configured to generate a reset pulse based on the set pulse, and a write driver block configured to write second data to a second non-volatile memory cell using the reset pulse, while writing first data to a first non-volatile memory cell using the set pulse.

Abstract translation: 非易失性存储器件包括被配置为产生置位脉冲的置位脉冲发生器，被配置为基于所设置的脉冲产生复位脉冲的复位脉冲发生器，以及被配置为将第二数据写入第二非易失性的写入驱动器块 使用复位脉冲的存储单元，同时使用设定脉冲将第一数据写入第一非易失性存储单元。

公开(公告)号：US08254158B2

公开(公告)日：2012-08-28

申请号：US12646345

申请日：2009-12-23

Applicant: Yong-Jun Lee ,  Kwangjin Lee ,  Taek-Sung Kim ,  Kwangho Kim ,  Wooyeong Cho ,  Hyunho Choi ,  Hye-Jin Kim ,  Qi Wang

Inventor： Yong-Jun Lee ,  Kwangjin Lee ,  Taek-Sung Kim ,  Kwangho Kim ,  Wooyeong Cho ,  Hyunho Choi ,  Hye-Jin Kim ,  Qi Wang

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2213/72

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Abstract translation: 在一个实施例中，半导体器件包括非易失性存储单元阵列，被配置为写入非易失性存储单元阵列的写入电路和控制电路。 控制电路被配置为存储至少一个擦除指示符。 擦除指示符与非易失性存储单元阵列的至少一部分相关联并且指示逻辑状态。 控制电路被配置为在非易失性存储单元阵列的相关部分的擦除操作期间，控制写入电路将由擦除指示符指示的逻辑状态写入非易失性存储单元阵列。

公开(公告)号：US08228720B2

公开(公告)日：2012-07-24

申请号：US12556787

申请日：2009-09-10

Applicant: Byung-Gil Choi ,  Hye-Jin Kim

Inventor： Byung-Gil Choi ,  Hye-Jin Kim

IPC: G11C7/04 ,  G11C8/08 ,  G11C11/21 ,  G11C8/10

CPC classification number: G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

Abstract: A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.

Abstract translation: 非易失性存储器件可以包括存储单元阵列，该存储单元阵列具有以矩阵形式布置的多个非易失性存储单元，包括多行非易失性存储单元。 多个字线中的每一个可以与矩阵的相应行的非易失性存储器单元耦合。 行解码器可以耦合到多个字线，其中行解码器被配置为使用具有响应于温度变化调节的电平的行偏置来禁用至少一个字线。 这种非易失性存储器件可以以减少的待机电流工作。

公开(公告)号：US08134866B2

公开(公告)日：2012-03-13

申请号：US12652842

申请日：2010-01-06

Applicant: Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

Inventor： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Abstract translation: 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US20110068481A1

公开(公告)日：2011-03-24

申请号：US12872448

申请日：2010-08-31

Applicant: Sung-Kyu PARK ,  Tae-Sung Park ,  Kyung-Man Kim ,  Hye-Jin Kim

Inventor： Sung-Kyu PARK ,  Tae-Sung Park ,  Kyung-Man Kim ,  Hye-Jin Kim

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括下封装，其包括下基板，安装在下基板上的下半导体芯片，并且包括再分布，以及模制下半导体芯片的模制层，上封装，包括上基板和上半导体芯片， 上部衬底，其中上部封装堆叠在下部封装上。 所述半导体封装还包括电连接器，所述电互连器从所述上衬底延伸到所述模制层中并且连接到所述重新分配以将所述上部和下部封装彼此电连接;以及虚设互连器，其从所述上衬底延伸到所述模制层中以物理耦合 上下包装彼此。

公开(公告)号：US07881145B2

公开(公告)日：2011-02-01

申请号：US12453872

申请日：2009-05-26

Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

IPC: G11C8/00

CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

Abstract translation: 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。