公开(公告)号：US20170317042A1

公开(公告)日：2017-11-02

申请号：US15592941

申请日：2017-05-11

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US20150214095A1

公开(公告)日：2015-07-30

申请号：US14163694

申请日：2014-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Martin Mischitz ,  Manfred Schneegans ,  Markus Heinrici

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L21/7688 ,  H01L21/0272 ,  H01L21/288 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53228 ,  H01L23/5328 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for producing a metal layer on a wafer is described. In one embodiment the method comprises providing a semiconductor wafer including a coating, printing a metal particle paste on the semiconductor wafer thereby forming a metal layer and heating the metal layer in a reductive gas for sintering the metal particle paste or for annealing a sintered metal particle paste in an oven.

Abstract translation: 对晶片上的金属层的制造方法进行说明。 在一个实施方案中，该方法包括提供包括涂层的半导体晶片，在半导体晶片上印刷金属颗粒糊料，从而形成金属层，并且在用于烧结金属颗粒糊料的还原性气体中加热金属层或者使烧结金属颗粒退火 贴在烤箱里

公开(公告)号：US20140264865A1

公开(公告)日：2014-09-18

申请号：US13803988

申请日：2013-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Schneegans ,  Juergen Foerster

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/7685 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device may include: a barrier layer; an adhesion layer disposed over the barrier layer; a metallization layer disposed over the adhesion layer, wherein the metallization layer is part of a final metallization level of the semiconductor device.

Abstract translation: 半导体器件可以包括：阻挡层; 设置在阻挡层上的粘附层; 设置在所述粘合层上的金属化层，其中所述金属化层是所述半导体器件的最终金属化水平的一部分。

公开(公告)号：US08816500B2

公开(公告)日：2014-08-26

申请号：US13715868

申请日：2012-12-14

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Ivan Nikitin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/562 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.

Abstract translation: 半导体器件包括半导体芯片，其包括第一主面和第二主面，其中第二主面是半导体芯片的背面。 此外，半导体器件包括布置在半导体芯片的第二主面的第一区域上的导电层，特别是导电层。 此外，半导体器件包括布置在半导体芯片的第二主面的第二区域上的聚合物结构，其中第二区域是半导体芯片的第二主面的周边区域，并且第一区域与第二区域的第二区域相邻 地区。

公开(公告)号：US20140167266A1

公开(公告)日：2014-06-19

申请号：US13715868

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Schneegans ,  Ivan Nikitin

IPC: H01L21/50 ,  H01L23/29

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/562 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.

Abstract translation: 半导体器件包括半导体芯片，其包括第一主面和第二主面，其中第二主面是半导体芯片的背面。 此外，半导体器件包括布置在半导体芯片的第二主面的第一区域上的导电层，特别是导电层。 此外，半导体器件包括布置在半导体芯片的第二主面的第二区域上的聚合物结构，其中第二区域是半导体芯片的第二主面的周边区域，并且第一区域与第二区域的第二区域相邻 地区。

公开(公告)号：US20140167224A1

公开(公告)日：2014-06-19

申请号：US13715922

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Schneegans ,  Bernhard Weidgans ,  Franco Mariani ,  Alexander Heinrich

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L23/3677 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/45 ,  H01L2221/68327 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83191 ,  H01L2224/83365 ,  H01L2224/8382 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract translation: 半导体器件包括具有第一主面和第二主面的半导体芯片。 第二主面是半导体芯片的背面。 第二主面包括第一区域和第二区域。 第二区域是第二主面的周边区域，第一区域的高度和第二区域的高度不同。 第一区域可以用金属填充，并且可以被平坦化到与第二区域相同的水平。

公开(公告)号：US20140117509A1

公开(公告)日：2014-05-01

申请号：US13661810

申请日：2012-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Schneegans ,  Juergen Foerster ,  Bernhard Weidgans ,  Norbert Urbansky ,  Tilo Rotth

IPC: H01L21/768 ,  C23C14/34 ,  H01L23/48 ,  H01L21/3205 ,  H01L29/06

CPC classification number: H01L21/2855 ,  C23C14/14 ,  C23C14/34 ,  C23C14/3414 ,  C23C14/3492 ,  C23C14/54 ,  H01L21/76877

Abstract: Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer.

Abstract translation: 公开了各种技术，方法和装置，其中金属沉积在基板上，并且金属对基板引起的应力受到限制，例如限制晶片的弯曲。