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公开(公告)号：US20180300098A1
公开(公告)日：2018-10-18
申请号：US15489096
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Altug Koker , Michael Apodaca , Kai Xiao , Jeffery S. Boles , Adam T. Lake , David M. Cimini , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Jacek Kwiatkowski , Philip R. Laws , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Wenyin Fu , Nikos Kaburlasos , Prasoonkumar Surti , Bhushan M. Borole
Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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公开(公告)号：US20180300074A1
公开(公告)日：2018-10-18
申请号：US15488723
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Kamal Sinha , Bhushan M. Borole , Altug Koker , Joydeep Ray , Wenyin Fu
Abstract: Power for on-die heavily used local memories in general purpose graphics processing unit (GPGPU) applications may be reduced by using low latency read and high latency write operations. Power consumption in read heavy graphic operations can be reduced using a small memory footprint design with possible reduction of hot spotting in some embodiments.
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公开(公告)号：US20180284868A1
公开(公告)日：2018-10-04
申请号：US15477029
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
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34.发明授权公开(公告)号：US12007824B2
公开(公告)日：2024-06-11
申请号：US17517090
申请日：2021-11-02
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
IPC: G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/36
CPC classification number: G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/363 , G09G5/366 , G09G2310/066 , G09G2310/08 , G09G2340/02 , G09G2360/06 , G09G2360/08 , G09G2370/022 , G09G2370/16
Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
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公开(公告)号：US11263720B2
公开(公告)日：2022-03-01
申请号：US16985329
申请日：2020-08-05
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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Patent Agency Ranking
公开(公告)号：US11176990B2
公开(公告)日：2021-11-16
申请号：US17018071
申请日：2020-09-11
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhishek R. Appu
IPC: G11C7/00 , G11C11/4094 , G06F9/30 , G06F12/0868 , G06F12/1027 , G11C11/4074 , G11C11/4093 , G06F13/40 , G06F9/38 , G11C11/419 , G06F12/0897 , G06F12/109 , G06F3/06 , G06F12/08
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US20210294560A1
公开(公告)日：2021-09-23
申请号：US17162864
申请日：2021-01-29
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Altug Koker , Michael Apodaca , Kai Xiao , Jeffery S. Boles , Adam T. Lake , David M. Cimini , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Jacek Kwiatkowski , Philip R. Laws , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Wenyin Fu , Nikos Kaburlasos , Prasoonkumar Surti , Bhushan M. Borole
Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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公开(公告)号：US20210109589A1
公开(公告)日：2021-04-15
申请号：US17006883
申请日：2020-08-30
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall , Deepak S. Vembar , Abhishek R. Appu , Ankur N. Shah
IPC: G06F1/3287 , G06F1/3234
Abstract: Methods and apparatus relating to techniques for shutting down one or more GPU (Graphics Processing Unit) components in response to unchanged scene detection are described. In one embodiment, one or more components of a processor enter a low power consumption state in response to a determination that a scene to be displayed is static. The static scene is displayed on a display device (e.g., based on information to be retrieved from memory) for as long as no change to the static scene is detected. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20210035257A1
公开(公告)日：2021-02-04
申请号：US16985329
申请日：2020-08-05
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US10817012B2
公开(公告)日：2020-10-27
申请号：US16527165
申请日：2019-07-31
Applicant: Intel Corporation
Inventor： Iqbal R. Rajwani , Altug Koker , Bhushan M. Borole , Kamal Sinha , Abhishek R. Appu , Anupama A. Thaploo , Sunil Nekkanti , Wenyin Fu
IPC: G06F1/06 , G06F1/08 , H03K19/09 , G06F9/38 , G06F13/16 , H03K19/096 , G06T1/60 , G06F9/30 , G06F1/14
Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.
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