公开(公告)号：US10990155B2

公开(公告)日：2021-04-27

申请号：US16663658

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US20200272513A1

公开(公告)日：2020-08-27

申请号：US16740794

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunther ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US10739842B2

公开(公告)日：2020-08-11

申请号：US15477046

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Alexander B. Uan-Zo-Li ,  Muhammad Abozaed ,  Efraim Rotem ,  Tod F. Schiff ,  James G. Hermerding, II ,  Chee Lim Nge

IPC: G06F1/00 ,  G06F1/3296 ,  G06F15/76 ,  G06F1/30 ,  G06F1/3215 ,  G06F1/3287 ,  G06F15/78

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

公开(公告)号：US10678319B2

公开(公告)日：2020-06-09

申请号：US16252012

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC: G06F1/32 ,  G06F15/76 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3293 ,  G06F30/34 ,  G06F119/06 ,  G06F119/08

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US20200012329A1

公开(公告)日：2020-01-09

申请号：US16546441

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US10429919B2

公开(公告)日：2019-10-01

申请号：US15635307

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US10429912B2

公开(公告)日：2019-10-01

申请号：US15846161

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Krishnakanth Sistla ,  Martin Rowland ,  Efraim Rotem ,  Brian J. Griffith ,  Ankush Varma ,  Anupama Suryanarayanan

IPC: G06F1/26 ,  G06F1/329 ,  G06F1/3203 ,  G06F1/3234

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

公开(公告)号：US10423202B2

公开(公告)日：2019-09-24

申请号：US15093042

申请日：2016-04-07

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Tod F. Schiff ,  Doron Rajwan ,  Jeffrey M. Jull ,  James G. Hermerding, II ,  Nir Rosenzweig ,  Maytal Toledano ,  Alexander B. Uan-Zo-Li

IPC: G06F1/26 ,  G08B21/18 ,  G06F1/3212 ,  G06F1/324 ,  G08B25/08

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

公开(公告)号：US10372197B2

公开(公告)日：2019-08-06

申请号：US15367330

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/26 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/32

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

公开(公告)号：US20190155606A1

公开(公告)日：2019-05-23

申请号：US16259880

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

IPC: G06F9/30 ,  G06F9/455 ,  G06F9/38 ,  G06F11/34 ,  G06F1/3234

Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.