公开(公告)号：US11934934B2

公开(公告)日：2024-03-19

申请号：US15488551

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Elmoustapha Ould- Ahmed-Vall ,  Barath Lakshmanan ,  Ben J. Ashbaugh ,  Jingyi Jin ,  Jeremy Bottleson ,  Mike B. Macpherson ,  Kevin Nealis ,  Dhawal Srivastava ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Altug Koker ,  Abhishek R. Appu

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/082 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06N3/063 ,  G06N3/082 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

Abstract: An apparatus to facilitate optimization of a convolutional neural network (CNN) is disclosed. The apparatus includes optimization logic to receive a CNN model having a list of instructions and including pruning logic to optimize the list of instructions by eliminating branches in the list of instructions that comprise a weight value of 0.

公开(公告)号：US20230401668A1

公开(公告)日：2023-12-14

申请号：US18456235

申请日：2023-08-25

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/084 ,  G06F9/30 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N3/044 ,  G06N3/045 ,  G06N20/00

CPC classification number: G06T1/20 ,  G06F7/483 ,  G06N3/084 ,  G06F9/30185 ,  G06F9/30014 ,  G06N3/063 ,  G06F9/5044 ,  G06F9/3863 ,  G06N3/044 ,  G06N3/045 ,  G06N20/00 ,  G06F3/14

Abstract: One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

公开(公告)号：US11748298B2

公开(公告)日：2023-09-05

申请号：US17826674

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

CPC classification number: G06F15/8007 ,  G06F9/3004 ,  G06F13/00 ,  G06F13/4027 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US20220366527A1

公开(公告)日：2022-11-17

申请号：US17871781

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  DUKHWAN Kim

IPC: G06T1/20 ,  G06F9/46 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning. A method of embodiments, as described herein, includes limiting execution of workloads for the respective contexts of a plurality of contexts to a specified subset of a plurality of processing resources of a processing system according to physical resource slices of the processing system that are associated with the respective contexts of the plurality of contexts.

公开(公告)号：US11360933B2

公开(公告)日：2022-06-14

申请号：US16744407

申请日：2020-01-16

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US11138686B2

公开(公告)日：2021-10-05

申请号：US16446265

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00 ,  G06F3/14 ,  G06T1/60 ,  G06T15/00

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.

公开(公告)号：US10540318B2

公开(公告)日：2020-01-21

申请号：US15482796

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F13/40 ,  G06T1/20 ,  G06F13/00 ,  G06F9/30 ,  G06F15/80 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US20190304053A1

公开(公告)日：2019-10-03

申请号：US16446265

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06N20/00 ,  G06F7/483

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.

公开(公告)号：US20190206020A1

公开(公告)日：2019-07-04

申请号：US16197821

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N20/00

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/3863 ,  G06F9/5044 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06T1/60 ,  G06T15/005

Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction. The at least one single instruction is to cause at least a portion of the GPU to perform a floating point operation on input having differing precisions. The floating point operation is a two-dimensional matrix multiply and accumulate operation.

公开(公告)号：US20180307983A1

公开(公告)日：2018-10-25

申请号：US15494948

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Narayan Srinivasa ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Ben Ashbaugh ,  Prasoonkumar Surti ,  Feng Chen ,  Barath Lakshmanan ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Linda L. Hurd ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Dukhwan Kim ,  Altug Koker ,  Nadathur Rajagopalan Satish

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/082

Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.