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    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH
    31.
    发明公开
    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH 审中-公开

    公开(公告)号：US20240223167A1

    公开(公告)日：2024-07-04

    申请号：US18091970

    申请日：2022-12-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Mark A. Anders ,  Ram K. Krishnamurthy

    IPC: H03K4/94 ,  H03K3/037

    CPC classification number: H03K4/94 ,  H03K3/037 ,  H03K19/20

    Abstract: Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

    HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE
    34.
    发明申请
    HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE 有权

    公开(公告)号：US20220214988A1

    公开(公告)日：2022-07-07

    申请号：US17701593

    申请日：2022-03-22

    Applicant: Intel Corporation

    Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

    IPC: G06F13/40 ,  H04L49/10 ,  H04L12/54

    Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

    Reconfigurable interconnect structure in integrated circuits
    37.
    发明授权
    Reconfigurable interconnect structure in integrated circuits 有权

    公开(公告)号：US10944402B1

    公开(公告)日：2021-03-09

    申请号：US16791559

    申请日：2020-02-14

    Applicant: Intel Corporation

    Inventor： SeongJong Kim ,  Mark A. Anders ,  Himanshu Kaul

    IPC: H03K19/17756 ,  H01L23/522

    Abstract: Some embodiments include apparatuses having a first circuit path including drive units coupled in series between a first node and a first additional node, a second circuit path including drive units coupled in series between a second node and a second additional node, each drive unit of the driver units of the first circuit path and the second circuit path including an inverter, and a transmission gate circuit including an input node and an output node coupled to an input node and an output node, respectively, of the inverter; and control circuitry to provide control information to the transmission gate circuit of each of the driver units of the first circuit path and the second circuit path.

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