公开(公告)号：US20230305846A1

公开(公告)日：2023-09-28

申请号：US17703194

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30036 ,  G06F9/30029 ,  G06F9/3001 ,  G06F9/3802

Abstract: A method comprises fetching, by fetch circuitry, an encoded vectorized AND-XOR instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and a destination identifier, decoding, by decode circuitry, the decoded vectorized AND-XOR instruction to generate a decoded vectorized AND-XOR instruction, and executing, by execution circuitry, the decoded vectorized AND-XOR instruction to retrieve operands representing a product coefficient at an index position from the first source, a coefficient of a first polynomial from the second source, and a coefficient of a second polynomial from the third source, perform, in an atomic fashion, a vectorized AND-XOR operation to generate updated value of the product coefficient, and store the product coefficient of the output polynomial in a register file accessible to the execution circuitry.

公开(公告)号：US11770258B2

公开(公告)日：2023-09-26

申请号：US17562461

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/3239 ,  H04L9/0869 ,  H04L9/3247 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

公开(公告)号：US11580234B2

公开(公告)日：2023-02-14

申请号：US16709612

申请日：2019-12-10

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  David M. Durham

IPC: G06F21/00 ,  G06F21/60 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/48 ,  G06F21/72 ,  H04L9/06 ,  G06F12/06 ,  G06F12/0875 ,  G06F21/79 ,  G06F9/455 ,  G06F12/0811 ,  G06F21/12 ,  H04L9/08 ,  G06F12/14 ,  G06F9/32 ,  G06F9/50 ,  G06F12/02 ,  H04L9/14 ,  G06F21/62

Abstract: In one embodiment, a processor includes a memory hierarchy and a core coupled to the memory hierarchy. The memory hierarchy stores encrypted data, and the core includes circuitry to access the encrypted data stored in the memory hierarchy, decrypt the encrypted data to yield decrypted data, perform an entropy test on the decrypted data, and update a processor state based on a result of the entropy test. The entropy test may include determining a number of data entities in the decrypted data whose values are equal to one another, determining a number of adjacent data entities in the decrypted data whose values are equal to one another, determining a number of data entities in the decrypted data whose values are equal to at least one special value from a set of special values, or determining a sum of n highest data entity value frequencies.

公开(公告)号：US11575515B2

公开(公告)日：2023-02-07

申请号：US17133558

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj Sastry

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/08 ,  G06F8/71

Abstract: A method comprises maintaining, for at least one remote device, a security footprint and a verified version of a software stack for the remote device, generating an attestation initiation token that includes a nonce to be used to generate an XMSS signature for attestation of the remote device, sending the attestation initiation token to the remote device, receiving, from the remote device, a modified message representative including a hash of a current version of a software stack for the remote device and an indicator of a version number of the current version of the software stack for the remote device, validating the hash, and in response to a determination that the hash is valid, generating an XMSS signature using the security footprint and the current version of a software stack for the remote device and a security footprint for the apparatus.

公开(公告)号：US11522678B2

公开(公告)日：2022-12-06

申请号：US17342271

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Luis Kida ,  Reshma Lal

IPC: H04L29/06 ,  G06F21/00 ,  H04L9/06 ,  H04L9/08

Abstract: Technologies for secure data transfer of MMIO data between a processor and an accelerator. A MIMO security engine includes a first block cipher pipeline to encrypt a count using a key; a first exclusive-OR (XOR) to generate a first XOR result of the encrypted count and a length multiplied by an authentication key; a second block cipher pipeline to encrypt (count+1) using the key; a second XOR to generate a second XOR result of plaintext data and the encrypted (count+1); a plurality of Galois field multipliers (GFMs) to perform Galois field multiplication on additional authenticated data (AAD), powers of the authentication key, and ciphertext data; and a plurality of exclusive-ORs (XORs) to combine results of the GFMs and the first XOR result to generate an authentication tag. Other embodiments are described and claimed.

公开(公告)号：US11429580B2

公开(公告)日：2022-08-30

申请号：US16912378

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael LeMay ,  David M. Durham

IPC: G06F16/22 ,  G06F16/2457 ,  G06F16/2455 ,  G06F9/38 ,  G06F21/60 ,  G06F21/62 ,  H03M13/00

Abstract: Embodiments are directed to collision-free hashing for accessing cryptographic computing metadata and for cache expansion. An embodiment of an apparatus includes one or more processors to compute a plurality of hash functions that combine additions, bit-level reordering, bit-linear mixing, and wide substitutions, wherein each of the plurality of hash functions differs in one of the additions, the bit-level reordering, the wide substitutions, or the bit-linear mixing; and access a hash table utilizing results of the plurality of hash functions.

公开(公告)号：US11321469B2

公开(公告)日：2022-05-03

申请号：US16724105

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael LeMay ,  David M. Durham ,  Stanislav Shwartsman

IPC: G06F9/30 ,  G06F12/06 ,  G06F21/79 ,  H04L9/08 ,  G06F9/50 ,  H04L9/14 ,  G06F9/48 ,  H04L9/06 ,  G06F9/455 ,  G06F21/60 ,  G06F12/0897 ,  G06F21/72 ,  G06F12/0875 ,  G06F12/0811 ,  G06F21/12 ,  G06F12/14 ,  G06F9/32 ,  G06F12/02 ,  G06F21/62

Abstract: In one embodiment, a processor of a cryptographic computing system includes data cache units storing encrypted data and circuitry coupled to the data cache units. The circuitry accesses a sequence of cryptographic-based instructions to execute based on the encrypted data, decrypts the encrypted data based on a first pointer value, executes the cryptographic-based instruction using the decrypted data, encrypts a result of the execution of the cryptographic-based instruction based on a second pointer value, and stores the encrypted result in the data cache units. In some embodiments, the circuitry generates, for each cryptographic-based instruction, at least one encryption-based microoperation and at least one non-encryption-based microoperation. The circuitry also schedules the at least one encryption-based microoperation and the at least one non-encryption-based microoperation for execution based on timings of the encryption-based microoperation.

公开(公告)号：US11303429B2

公开(公告)日：2022-04-12

申请号：US16455950

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US20220108039A1

公开(公告)日：2022-04-07

申请号：US17551961

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

公开(公告)号：US20220094518A1

公开(公告)日：2022-03-24

申请号：US17025344

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  H04L9/30

Abstract: Embodiments are directed to low circuit depth homomorphic encryption evaluations. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, determine two coefficients of the ciphertext for HE evaluation, input the two coefficients as a first operand and a second operand to a pipeline multiplier for low circuit depth HE evaluation, perform combinatorial multiplication between the first operand and portions of the second operand, accumulate results of the combinatorial multiplication at each stage of the pipeline multiplier, and perform reduction with Mersenne prime modulus on a resulting accumulated output of the combinatorial multipliers of the pipeline multiplier.