公开(公告)号：US20070148973A1

公开(公告)日：2007-06-28

申请号：US11319895

申请日：2005-12-28

Applicant: Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

Inventor： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

IPC: H01L21/302 ,  B44C1/22 ,  H01L21/461

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

Abstract translation: 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。 在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以产生 类似的最终结构。

公开(公告)号：US07234444B2

公开(公告)日：2007-06-26

申请号：US11640408

申请日：2006-12-18

Applicant: Kunio Nanba ,  Kazuto Maeda ,  Koji Hashimoto

Inventor： Kunio Nanba ,  Kazuto Maeda ,  Koji Hashimoto

IPC: F02D9/08

CPC classification number: F02D9/1045 ,  F02M26/50 ,  F02M26/54 ,  F02M26/70 ,  F02M26/73

Abstract: Emission gas recycling equipment includes a passage for recycling a part of an emission gas and a control valve for controlling an amount of the part of the emission gas. The control valve includes: a housing having a pipe portion; a butterfly valve accommodated in the pipe portion rotatable in a first direction and a second direction; a seal ring for sealing a clearance; and valve open/close operation means for stopping the butterfly valve at the valve full close position after the valve open/close operation means operates the butterfly valve to open and to close equal to or more than one cycle across the valve full close position at the time when the engine stops or after the engine stops.

公开(公告)号：US20070095334A1

公开(公告)日：2007-05-03

申请号：US11640408

申请日：2006-12-18

Applicant: Kunio Nanba ,  Kazuto Maeda ,  Koji Hashimoto

Inventor： Kunio Nanba ,  Kazuto Maeda ,  Koji Hashimoto

IPC: F02M25/07 ,  F02B47/08 ,  F16K31/02

CPC classification number: F02D9/1045 ,  F02M26/50 ,  F02M26/54 ,  F02M26/70 ,  F02M26/73

Abstract: Emission gas recycling equipment includes a passage for recycling a part of an emission gas and a control valve for controlling an amount of the part of the emission gas. The control valve includes: a housing having a pipe portion; a butterfly valve accommodated in the pipe portion rotatable in a first direction and a second direction; a seal ring for sealing a clearance; and valve open/close operation means for stopping the butterfly valve at the valve full close position after the valve open/close operation means operates the butterfly valve to open and to close equal to or more than one cycle across the valve full close position at the time when the engine stops or after the engine stops.

Abstract translation: 排放气体回收设备包括用于回收一部分排放气体的通道和用于控制排出气体的一部分量的控制阀。 控制阀包括：具有管部分的壳体; 容纳在沿第一方向和第二方向旋转的管部中的蝶阀; 用于密封间隙的密封环; 以及阀打开/关闭操作装置，用于在阀打开/关闭操作装置操作蝶阀以打开和关闭等于或大于一个循环的阀完全关闭位置时将蝶阀停止在阀完全关闭位置 发动机停止或发动机停止后的时间。

公开(公告)号：US07208423B2

公开(公告)日：2007-04-24

申请号：US10107298

申请日：2002-03-28

Applicant: Koji Hashimoto ,  Soichi Inoue ,  Kazuhiro Takahata ,  Kei Yoshikawa

Inventor： Koji Hashimoto ,  Soichi Inoue ,  Kazuhiro Takahata ,  Kei Yoshikawa

IPC: H01L21/302 ,  G03C5/00 ,  B44C1/22

CPC classification number: G03F7/0035 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897

Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.

Abstract translation: 在工作薄膜（3）上的硬掩模材料膜（4）上的曝光分辨率的限制的尺寸形成抗蚀剂图案（5）。 使用抗蚀剂图案（5）作为掩模来处理材料膜（4）。 由此形成硬掩模图案（6）。 由此，在非选择区域（6b）上形成具有开口（7a）的抗蚀剂图案（7），掩模图案中的选择区域（6a）通过该开口暴露。 仅通过开口（7a）暴露的掩模图案（6a）通过进行选择蚀刻而变薄，通过使用掩模图案（6）蚀刻工作膜（3）。 由此形成工作胶片图案（8），其包括具有限制曝光分辨率的尺寸宽度的宽图案部分（8a）和尺寸不大于该尺寸的尺寸的纤薄图案部分（8a） 曝光分辨率的限制。

公开(公告)号：US20070057657A1

公开(公告)日：2007-03-15

申请号：US11331017

申请日：2006-01-13

Applicant: Koji Hashimoto ,  Manabu Yamashita

Inventor： Koji Hashimoto ,  Manabu Yamashita

IPC: G05F1/00

CPC classification number: H02M3/158 ,  H02M2001/009 ,  Y10T307/383

Abstract: A first output voltage Vcc is obtained via a first switching element from an external power supply, and a second output voltage Vme via a second switching element cascade-connected to the first switching element. The first switching element has a base current continuously controlled by a first comparator/amplifier to maintain the voltage Vcc at a predetermined value. The second switching element has a base current continuously controlled by a second comparator/amplifier to maintain the voltage Vme at a predetermined value. A third switching element connected in parallel to the first switching element and controlled by a duty-factor control circuit makes a bypass power supply to maintain a current flowing through the first switching element not more than a predetermined value. Thus, a constant voltage control device obtaining two types of stabilized voltages from external power supply of large voltage variation can reduce power consumption and improve voltage control accuracy.

Abstract translation: 经由第一开关元件从外部电源获得第一输出电压Vcc，并且经由与第一开关元件级联连接的第二开关元件获得第二输出电压Vme。 第一开关元件具有由第一比较器/放大器连续控制的基极电流，以将电压Vcc保持在预定值。 第二开关元件具有由第二比较器/放大器连续控制的基极电流，以将电压Vme保持在预定值。 与第一开关元件并联并由占空比控制电路控制的第三开关元件使得旁路电源将流过第一开关元件的电流维持在不超过预定值。 因此，从具有大电压变化的外部电源获得两种类型的稳定电压的恒压控制装置可以降低功耗并提高电压控制精度。

公开(公告)号：US20070050741A1

公开(公告)日：2007-03-01

申请号：US11505917

申请日：2006-08-18

Applicant: Ryuji Ogawa ,  Koji Hashimoto

Inventor： Ryuji Ogawa ,  Koji Hashimoto

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.

Abstract translation: 集成电路图案的验证方法包括提取不大于预设图案尺寸的图案，从提取的图案中提取作为光刻仿真的目标的图案边缘，以及对提取的图案边缘进行光刻模拟以验证 集成电路图案。

公开(公告)号：US07180012B2

公开(公告)日：2007-02-20

申请号：US10493437

申请日：2003-08-25

Applicant: Michiaki Tsuneoka ,  Koji Hashimoto ,  Masaaki Hayama ,  Takeo Yasuho

Inventor： Michiaki Tsuneoka ,  Koji Hashimoto ,  Masaaki Hayama ,  Takeo Yasuho

IPC: H01L23/28

CPC classification number: H01L23/3121 ,  H01L23/13 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/403 ,  H01L2924/00

Abstract: A module component with a good shield effect and a low height including a circuit board having mounted thereon a mount device including an electronic part. The device is sealed with a sealing body having a metal film formed on the sealing body surface. A ground pattern is formed at the outer periphery of the principal surface of the circuit board. The metal film is conductively connected with the ground pattern.

Abstract translation: 具有良好屏蔽效果和低高度的模块部件，包括其上安装有包括电子部件的安装装置的电路板。 该装置用形成在密封体表面上的金属膜的密封体密封。 在电路板的主表面的外周形成接地图案。 金属膜与接地图形导电连接。

公开(公告)号：US07161252B2

公开(公告)日：2007-01-09

申请号：US10485540

申请日：2003-06-16

Applicant: Michiaki Tsuneoka ,  Koji Hashimoto ,  Masaaki Hayama ,  Takeo Yasuho

Inventor： Michiaki Tsuneoka ,  Koji Hashimoto ,  Masaaki Hayama ,  Takeo Yasuho

IPC: H01L23/28

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/60 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/284 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A module includes a component, a circuit board having the component mounted thereon, a first grounding pattern formed on an outermost periphery of a surface portion of the circuit board; a first sealer provided on the circuit board and having a dimension projected on the circuit board, and a metal film covering the sealer and connected to the grounding pattern. The dimension of the first dealer is smaller than an outside dimension of the circuit board. The first sealer is made of first resin and sealing the component. The module has a low profile and is adequately shielded.

Abstract translation: 模块包括部件，具有安装在其上的部件的电路板，形成在电路板的表面部分的最外周上的第一接地图案​​; 设置在电路板上并具有投影在电路板上的尺寸的第一密封器，以及覆盖密封件并连接到接地图案的金属膜。 第一经销商的尺寸小于电路板的外部尺寸。 第一个封口机由第一个树脂制成并密封组件。 该模块具有低外形并且被充分屏蔽。

公开(公告)号：US07141474B2

公开(公告)日：2006-11-28

申请号：US11008531

申请日：2004-12-10

Applicant: Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

Inventor： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

Abstract: A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an opening in a part of the inter-gate insulating layer; depositing a control gate electrode on the inter-gate insulating layer and an exposed portion of the first conductive layer by the opening; and forming the gate electrodes of the memory cell transistors and the gate electrodes of the select transistors by utilizing the etching processes of the control gate electrode, the inter-gate insulating layer and the first conductive layer, wherein the select transistors include at least a part of the exposed portion of the first conductive layer.

Abstract translation: 一种制造非易失性半导体存储器的方法，包括以下步骤：在半导体衬底上依次形成栅极绝缘层和浮置栅极的第一导电层; 沉积栅极间绝缘层; 在所述栅极绝缘层的一部分中形成开口; 通过所述开口在所述栅极间绝缘层上沉积控制栅极电极和所述第一导电层的暴露部分; 以及通过利用所述控制栅电极，所述栅极间绝缘层和所述第一导电层的蚀刻工艺，形成所述存储单元晶体管的栅电极和所述选择晶体管的栅电极，其中所述选择晶体管至少包括一部分 的第一导电层的暴露部分。

公开(公告)号：US20060233560A1

公开(公告)日：2006-10-19

申请号：US11398726

申请日：2006-04-06

Applicant: Kinya Harada ,  Koji Hashimoto

Inventor： Kinya Harada ,  Koji Hashimoto

IPC: G03G15/08

CPC classification number: G03G15/0856 ,  G03G15/0862 ,  G03G15/0891 ,  G03G2215/0119 ,  G03G2221/183

Abstract: An image forming apparatus includes an image bearing member on which an electrostatic latent image is capable of being formed; a developer accommodating container for accommodating a developer for developing the electrostatic latent image; a detecting device for detecting a remaining amount of the developer in the developer accommodating container, wherein the detecting device detects the remaining amount during a period in which no image forming operation is performed; a developer feeding member for feeding and stirring the developer in the developer accommodating container, the developer stirring member being rotatable at a speed which is lower during detection of the remaining amount than when an image forming operation is performed, wherein the detecting device detects first, second and third developer remaining amounts in first, second and third remaining amount detecting periods, respectively, in the order named, and wherein an interval between the second detection period and the third detection period is changed on the basis of the first and second remaining amounts.

Abstract translation: 图像形成装置包括能够形成静电潜像的图像承载部件; 用于容纳用于显影静电潜像的显影剂的显影剂容纳容器; 用于检测显影剂容纳容器中的显影剂剩余量的检测装置，其中检测装置在不执行图像形成操作的时段期间检测剩余量; 用于在显影剂容纳容器中供给和搅拌显影剂的显影剂供给构件，显影剂搅拌构件可以在检测剩余量时比在执行图像形成操作时低的速度旋转，其中检测装置首先检测， 第二和第三显影剂剩余量分别按照所述的顺序分配在第一，第二和第三剩余量检测周期中，并且其中基于第一和第二剩余量改变第二检测周期和第三检测周期之间的间隔 。