公开(公告)号：US11043534B2

公开(公告)日：2021-06-22

申请号：US16735154

申请日：2020-01-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/24 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11553 ,  H01L27/1158 ,  H01L45/00

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

公开(公告)号：US20210174874A1

公开(公告)日：2021-06-10

申请号：US17027425

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US20210118508A1

公开(公告)日：2021-04-22

申请号：US17087166

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US20200066346A1

公开(公告)日：2020-02-27

申请号：US16667465

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US10515972B2

公开(公告)日：2019-12-24

申请号：US15685878

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/1158

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

公开(公告)号：US20190198109A1

公开(公告)日：2019-06-27

申请号：US15850708

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  G11C8/08 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  H01L45/00

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US10170189B2

公开(公告)日：2019-01-01

申请号：US15721007

申请日：2017-09-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US10043574B2

公开(公告)日：2018-08-07

申请号：US15907826

申请日：2018-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/12

Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.

公开(公告)号：US20180122481A1

公开(公告)日：2018-05-03

申请号：US15721007

申请日：2017-09-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/12 ,  G11C16/06 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US09922704B2

公开(公告)日：2018-03-20

申请号：US15189178

申请日：2016-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427

Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.