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    STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
    33.
    发明申请
    STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION 有权
    在具有连接配置中的设备的系统中的状态更改

    公开(公告)号：US20150301746A1

    公开(公告)日：2015-10-22

    申请号：US14755555

    申请日：2015-06-30

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

    IPC: G06F3/06

    CPC classification number: G06F13/102 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1684 ,  G06F13/4282 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

    Abstract translation: 本公开包括用于在具有以链式配置耦合的设备的系统中的状态改变的方法，设备和系统。 许多实施例包括以链式配置耦合到主机的主机和多个设备。 链接配置包括至少一个不直接耦合到主机的设备。 不直接耦合到主机的至少一个设备被配置为响应于从主机接收到命令而从第一通信状态改变到第二通信状态。

    Host controller
    35.
    发明授权
    Host controller 有权
    主机控制器

    公开(公告)号：US09043506B2

    公开(公告)日：2015-05-26

    申请号：US14055436

    申请日：2013-10-16

    Applicant: Micron Technology, Inc.

    Inventor： Peter Feeley ,  Robert N. Leibowitz ,  William H. Radke ,  Neal A. Galbo ,  Victor Y. Tsai

    IPC: G06F13/28 ,  G06F13/38

    CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/28 ,  G06F13/32 ,  G06F13/385 ,  G06F13/4282

    Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

    Abstract translation: 本公开包括用于控制存储器设备的方法，设备和系统。 用于控制存储器件实施例的一种方法包括将设备类相关信息和命令存储在主机系统存储器和主机控制器存储器中的一个或多个中，在主机控制器中的寄存器中设置指向该命令的指针， 通过主机控制器更多的主机系统内存和主机控制器内存与存储设备; 并用存储器件执行命令。

    Booting in systems having devices coupled in a chained configuration
    36.
    发明授权
    Booting in systems having devices coupled in a chained configuration 有权
    在具有以链接配置耦合的设备的系统中引导

    公开(公告)号：US09037842B2

    公开(公告)日：2015-05-19

    申请号：US14034852

    申请日：2013-09-24

    Applicant: Micron Technology, Inc

    Inventor： William H Radke ,  Victor Y Tsai ,  Peter Feeley ,  Neal A Galbo ,  Robert N Leibowitz

    IPC: G06F9/24 ,  G06F9/00 ,  G06F3/00 ,  G06F9/44

    CPC classification number: G06F9/4411 ,  G06F9/4401

    Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

    Abstract translation: 本公开包括用于在具有以链接配置耦合的设备的系统中引导的方法，设备和系统。 一个或多个实施例包括以链接配置耦合到主机的主机和多个设备，其中，多个设备中的至少一个是可引导设备，并且所述至少一个可启动设备不直接耦合到主机。

    Memory devices with different sized blocks of memory cells and methods
    37.
    发明授权
    Memory devices with different sized blocks of memory cells and methods 有权
    具有不同大小的存储器单元和方法的存储器件

    公开(公告)号：US09007831B2

    公开(公告)日：2015-04-14

    申请号：US13785210

    申请日：2013-03-05

    Applicant: Micron Technology, Inc.

    Inventor： Koji Sakui ,  Peter Feeley

    IPC: G11C16/04 ,  G11C16/10

    CPC classification number: G11C16/10 ,  G11C8/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418

    Abstract: In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of the block is coupled to a common first select line. The plurality of blocks includes N block sizes, where N may be an integer greater than or equal to three. N−1 blocks of one block size of the N block sizes collectively include a first number of second select lines. A group of blocks consisting of a respective block of each remaining block size of the N block sizes collectively include a second number of second select lines that is equal to the first number of select lines or that is less than the first number of second select lines.

    Abstract translation: 在一个实施例中，多个块的每个块包括相应的多个存储单元串，其中块的多个串中的每一个被耦合到相应的选择晶体管，并且其中每个选择晶体管耦合到多个 该块的串被耦合到公共的第一选择线。 多个块包括N个块大小，其中N可以是大于或等于3的整数。 N个块大小的一个块大小的N-1块共同地包括第一数量的第二选择线。 由N个块大小的每个剩余块大小的相应块组成的一组块集合地包括第二数量的第二选择线，其等于第一数量的选择线或小于第一数量的第二选择线 。

    MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE
    38.
    发明申请
    MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE 有权
    具有三个晶体管存储单元设备的存储器

    公开(公告)号：US20140347932A1

    公开(公告)日：2014-11-27

    申请号：US14455449

    申请日：2014-08-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Koji Sakui ,  Peter Feeley

    IPC: G11C16/04 ,  G11C16/10

    CPC classification number: G11C16/0408 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

    Abstract: Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device.

    Abstract translation: 公开了存储器，存储器件以及用于备份序列的方法。 在一个这样的存储器件中，检测电路和页缓冲器耦合在三晶体管存储单元器件和非易失性存储器器件之间。 启用/禁用门使得能够通过三晶体管存储单元设备或非易失性存储器件选择性地访问感测电路和页面缓冲器。

    METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES
    39.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES 有权
    用于调节设备中感应电压的方法，设备和系统

    公开(公告)号：US20130141985A1

    公开(公告)日：2013-06-06

    申请号：US13746689

    申请日：2013-01-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    IPC: G11C16/26

    CPC classification number: G11C16/28 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26

    Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

    Abstract translation: 本公开包括用于调整设备中的感测电压的方法，设备和系统。 一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作的控制器，以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压 用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。

    TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
    40.
    发明申请
    TRIM SETTING DETERMINATION FOR A MEMORY DEVICE 有权

    公开(公告)号：US20250166719A1

    公开(公告)日：2025-05-22

    申请号：US19028149

    申请日：2025-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Aswin Thiruvengadam ,  Daniel L. Lowrance ,  Peter Feeley

    IPC: G11C29/02 ,  G06F12/02 ,  G11C16/10 ,  G11C29/44

    Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

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