公开(公告)号：US20210034241A1

公开(公告)日：2021-02-04

申请号：US16530833

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Samir Mittal ,  Gurpreet Anand

IPC: G06F3/06 ,  G06N7/00 ,  G06F16/901

Abstract: Data blocks of a memory sub-system that have been accessed by a host system can be determined. An access pattern associated with the data blocks by the host system can be determined. A spatial characteristic for each respective pair of the data blocks of the memory sub-system can be received. A data graph can be generated with nodes that are based on the access pattern associated with the data blocks of the memory sub-system and edge values between the nodes that are based on the spatial characteristic for each respective pair of the data blocks of the memory sub-system.

公开(公告)号：US10782908B2

公开(公告)日：2020-09-22

申请号：US16054819

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Anirban Ray ,  Gurpreet Anand

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0811 ,  G06F13/16 ,  G06N3/08

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

公开(公告)号：US20200272530A1

公开(公告)日：2020-08-27

申请号：US16874011

申请日：2020-05-14

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Gurpreet Anand ,  Anirban Ray ,  Parag R. Maharana

IPC: G06F9/54 ,  G06F15/173 ,  G06N3/08 ,  G06F12/0864 ,  G06F13/42

Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

公开(公告)号：US20200081763A1

公开(公告)日：2020-03-12

申请号：US16123900

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F11/07 ,  G06F13/16 ,  G06F13/12

Abstract: A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.

公开(公告)号：US11663133B2

公开(公告)日：2023-05-30

申请号：US17824685

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Paul Stonelake ,  Samir Mittal ,  Gurpreet Anand

IPC: G06F12/0868 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/0868 ,  G06F3/0604 ,  G06F3/068 ,  G06F3/0653 ,  G06F3/0659 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

公开(公告)号：US11573901B2

公开(公告)日：2023-02-07

申请号：US17135207

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Samir Mittal ,  Gurpreet Anand ,  Parag R. Maharana

IPC: G06F12/0862 ,  G06F12/1009 ,  G06F12/0871 ,  G06F12/0873 ,  G06N3/08 ,  G06F9/455

Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.

公开(公告)号：US11567817B2

公开(公告)日：2023-01-31

申请号：US17335433

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/12 ,  G06F13/16

Abstract: A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

公开(公告)号：US11119679B2

公开(公告)日：2021-09-14

申请号：US16530833

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Samir Mittal ,  Gurpreet Anand

IPC: G06F3/06 ,  G06F16/901 ,  G06N7/00 ,  G06F12/02

Abstract: Data blocks of a memory sub-system that have been accessed by a host system can be determined. An access pattern associated with the data blocks by the host system can be determined. A spatial characteristic for each respective pair of the data blocks of the memory sub-system can be received. A data graph can be generated with nodes that are based on the access pattern associated with the data blocks of the memory sub-system and edge values between the nodes that are based on the spatial characteristic for each respective pair of the data blocks of the memory sub-system.

公开(公告)号：US20210240624A1

公开(公告)日：2021-08-05

申请号：US17239454

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Samir Mittal

IPC: G06F12/0806 ,  G06F3/06

Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

公开(公告)号：US11080210B2

公开(公告)日：2021-08-03

申请号：US16123907

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F11/00 ,  G06F13/16 ,  G06F13/42 ,  G06F11/07

Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.