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    METHODS OF FORMING MICROELECTRONIC DEVICES
    34.
    发明公开
    METHODS OF FORMING MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20230389318A1

    公开(公告)日：2023-11-30

    申请号：US18359792

    申请日：2023-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Justin D. Shepherdson ,  Chet E. Carter

    IPC: H10B43/27 ,  H10B43/50

    CPC classification number: H10B43/27 ,  H10B43/50

    Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    35.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20230389312A1

    公开(公告)日：2023-11-30

    申请号：US17751978

    申请日：2022-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Taehyun Kim

    IPC: H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed. Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings. Other embodiments, including structure, are disclosed.

    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells
    36.
    发明公开
    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells 审中-公开

    公开(公告)号：US20230337429A1

    公开(公告)日：2023-10-19

    申请号：US18212899

    申请日：2023-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Chet E. Carter

    IPC: H10B43/27 ,  H01L21/822 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    CPC classification number: H10B43/27 ,  H01L21/8221 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

    Memory arrays and methods used in forming a memory array
    40.
    发明授权
    Memory arrays and methods used in forming a memory array 有权

    公开(公告)号：US11411015B2

    公开(公告)日：2022-08-09

    申请号：US17151344

    申请日：2021-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Chet E. Carter

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/3213

    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.

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