公开(公告)号：US20140361423A1

公开(公告)日：2014-12-11

申请号：US14466923

申请日：2014-08-22

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/4832 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/33 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure.

Abstract translation: 半导体器件具有从基板延伸的多个主体的引线框架。 第一半导体管芯安装在引线框架的基板之间。 密封剂沉积在第一半导体管芯和基板上并且围绕引线框架的主体。 去除引线框架的主体上的密封剂的一部分，以在密封剂中形成暴露主体的第一开口。 互连结构形成在密封剂上方并延伸到引导框架的主体的第一开口中。 引导框架和主体被移除以在密封剂中形成对应于先前由主体占据的空间以露出互连结构的第二开口。 第二半导体管芯安装在第一半导体管芯上，凸块延伸到密封剂的第二开口中以电连接到互连结构。

公开(公告)号：US09721921B2

公开(公告)日：2017-08-01

申请号：US15012346

申请日：2016-02-01

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

公开(公告)号：US09406533B2

公开(公告)日：2016-08-02

申请号：US13929776

申请日：2013-06-27

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  KyungMoon Kim

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/831 ,  H01L2224/8385 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.

Abstract translation: 形成用于半导体器件和封装的导电和绝缘层的方法。 衬底上装有集成电路器件和互连结构，其中互连结构与集成电路器件相邻。 集成电路器件和互连结构的部分可以覆盖暴露一部分互连结构的封装。 导电材料通过沉积过程形成在互连结构的暴露部分上，然后进行加热过程以改变导电材料的化学性质。 任选地，可以并入分散过程。

公开(公告)号：US09362161B2

公开(公告)日：2016-06-07

申请号：US14220336

申请日：2014-03-20

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  NamJu Cho

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L21/768 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/19 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/153 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2224/08

Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.

Abstract translation: 半导体器件具有多个半导体管芯。 衬底设置有设置在衬底上的凸起。 第一预制绝缘膜设置在半导体管芯和衬底之间。 在半导体管芯和第一预制绝缘膜上形成互连结构。 凸块包括封装在镀铜中的铜芯。 第一预制绝缘膜包括玻璃布，玻璃纤维或玻璃填料。 衬底包括形成在衬底中并耦合到凸块的导电层。 半导体管芯设置在衬底的凸块之间。 凸块和半导体管芯嵌入在第一预制绝缘膜内。 去除第一预制绝缘膜的一部分以暴露凸块。 凸块将基板电连接到互连结构。

公开(公告)号：US09153476B2

公开(公告)日：2015-10-06

申请号：US13691464

申请日：2012-11-30

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  YeongIm Park ,  HyungMin Lee

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L21/76802 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49517 ,  H01L23/49527 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16245 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K1/185 ,  H05K3/4682 ,  H01L2224/82 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias.

Abstract translation: 具有多个接触垫的预制多芯片引线框安装在临时载体上。 第一半导体管芯安装在引线框架的接触焊盘之间的载体上。 第二半导体管芯安装在引线框架的接触焊盘上并且在第一管芯上方。 密封剂沉积在引线框架和第一和第二裸片上。 载体被移除。 第一互连结构形成在引线框架和第一管芯以及密封剂的第一表面上。 通过密封剂和引线框架切割通道以分离接触垫。 可以通过密封剂形成多个导电通孔。 第二互连结构形成在密封剂的与密封剂的第一表面相对的第二表面上。 第二互连结构电连接到导电通孔。

公开(公告)号：US20150279778A1

公开(公告)日：2015-10-01

申请号：US14228531

申请日：2014-03-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Bartholomew Liao ,  Sheila Marie L. Alvarez ,  HeeJo Chi ,  Kelvin Dao

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/3107 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die and encapsulant. A first channel including a first conductive surface is formed in the insulating layer by laser radiation. A laser-activated catalyst is infused in the insulating layer to form the first conductive surface in the first channel upon laser radiation. A vertical interconnect is formed through the encapsulant. A first conductive layer is formed in the first channel over the first conductive surface. A second channel including a second conductive surface is formed in the encapsulant by laser radiation. The catalyst is infused in the encapsulant to form the second conductive surface in the second channel upon laser radiation. A second conductive layer is formed in the second channel over the second conductive surface. An interconnect structure is formed over the first conductive layer.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 在半导体管芯和密封剂上形成绝缘层。 通过激光辐射在绝缘层中形成包括第一导电表面的第一通道。 在绝缘层中注入激光激活的催化剂，以在激光辐射时在第一通道中形成第一导电表面。 通过密封剂形成垂直互连。 第一导电层在第一通道上形成在第一导电表面上。 通过激光辐射在密封剂中形成包括第二导电表面的第二通道。 催化剂注入到密封剂中以在激光辐射下在第二通道中形成第二导电表面。 第二导电层在第二通道上形成在第二导电表面上。 在第一导电层上形成互连结构。

公开(公告)号：US20150004748A1

公开(公告)日：2015-01-01

申请号：US13929775

申请日：2013-06-27

Applicant: STATS ChipPAC, Ltd.

Inventor： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

IPC: H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4867 ,  H01L21/561 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/4917 ,  H01L2224/49173 ,  H01L2224/49176 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H05K1/092 ,  H05K3/125 ,  H05K3/1283 ,  H05K3/4685 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2203/095 ,  H05K2203/1194 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines.

Abstract translation: 形成用于半导体器件和封装的导电跳线迹线的方法。 衬底具有形成在其上的第一，第二和第三迹线，其中第一迹线位于第二和第三迹线之间。 第一条痕迹线可以用覆盖层隔离。 可以通过沉积工艺在第二和第三迹线之间和第一迹线上形成导电层，随后进行加热处理以改变导电层的化学性质。 所得到的导电层能够符合覆盖层并且用于在第二和第三迹线之间提供电连接。

公开(公告)号：US20130299982A1

公开(公告)日：2013-11-14

申请号：US13944825

申请日：2013-07-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

Abstract translation: 半导体器件具有安装在载体上的插入器。 插入器包括在安装到载体之前或之后形成的TSV。 在插入器中形成开口。 插入器可以具有通过第一阶梯部分的第一垂直传导路径和穿过第二阶梯部分的第二垂直传导路径的两级台阶部分。 第一和第二半导体管芯安装在插入件上。 第二管芯设置在插入件的开口内。 分立半导体部件可以安装在插入器上。 可以通过第二管芯或密封剂形成导电通孔。 密封剂沉积在第一和第二管芯和插入件上。 插入器的一部分可以被去除，使得密封剂围绕半导体器件的一侧形成。 互连结构形成在插入件和第二管芯上。