公开(公告)号：US20180285061A1

公开(公告)日：2018-10-04

申请号：US15938005

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung PARK ,  Chan-Yong JUNG ,  Ga-Jin SONG ,  Dong-Ho JANG

IPC: G06F3/16 ,  G06F3/0482 ,  G06F3/0484 ,  G06F3/0481

Abstract: Various embodiments of the present disclosure relate to an electronic device. The electronic device includes a housing, a touch screen display disposed on a surface of the housing, at least one wireless or wired communication circuit located inside the housing, a speaker exposed through the housing, at least one processor positioned inside the housing and operatively connected to the display, the communication circuit, and the speaker and a memory positioned inside the housing and operatively connected to the processor, wherein the memory stores instructions that, when executed, cause the at least one processor to detect that the electronic device is communicating with an external display device through the communication circuit, provide first data for rendering a first user interface on the external display device through the communication circuit responsive detecting that the electronic device is communicating with the external display device, determine whether the external display device can output audio data, in response that the external device can output audio data, provide second data configured to render a second user interface on the external display device through the communication circuit, wherein the second user interface allows a user to select one of the electronic device and the external display device for providing audio generated from or relayed through the electronic device, receive a selection of one of the electronic device and the external display device through the communication circuit or the touch screen display, and adapt an audio output path of the electronic device to provide the audio on the basis of the selection responsive to receiving the selection.

公开(公告)号：US20170347478A1

公开(公告)日：2017-11-30

申请号：US15490215

申请日：2017-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung PARK ,  Daeyoung NOH ,  Chankeun SONG ,  Minsung LEE ,  Yongseok LEE ,  Minsu JUNG ,  Sungjoo CHO ,  Youngsik CHOI ,  Minwoo YOO ,  Byounguk YOON ,  Jongchul CHOI

IPC: H05K5/02 ,  H04M1/02 ,  H05K7/14

CPC classification number: H05K5/0295 ,  H04B1/3816 ,  H04M1/0249 ,  H04M1/026 ,  H04M1/18 ,  H05K5/0217 ,  H05K7/1461

Abstract: An electronic device with a seal member is provided. The electronic device includes a tray configured to slide in and out of the electronic device, an opening, (e.g., a hole) formed at one side of the tray, for communicating outside of the electronic device, a socket disposed in the electronic device, the tray slides into or from the socket, and a seal member, disposed between the opening and the socket, for performing a waterproof and dustproof function. Various types of the seal member may be implemented.

公开(公告)号：US20150261683A1

公开(公告)日：2015-09-17

申请号：US14643046

申请日：2015-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok HONG ,  Byoungik KANG ,  Gilyoon KIM ,  Jinyoung PARK ,  Seungjin YANG ,  Jinyong JANG ,  Chunmok CHUNG ,  Jin CHOI

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0895

Abstract: Disclosed are a method and apparatus for controlling a cache memory in an electronic device. The apparatus includes a cache memory having cache lines, each of which includes tag information and at least two sub-lines. Each of the at least two sub-lines including a valid bit and a dirty bit. A control unit may analyze a valid bit of a sub-line corresponding to an address tag of data when a request for writing the data is sensed, determine based on activation or deactivation of the valid bit whether a cache hit or a cache miss occurs, and perform a control operation for allocating a sub-line according to a size of the requested data and write the data when the cache hit occurs.

Abstract translation: 公开了一种用于控制电子设备中的高速缓冲存储器的方法和装置。 该装置包括具有高速缓存行的高速缓冲存储器，每个高速缓存行包括标签信息和至少两个子行。 所述至少两条子线中的每一条包括有效位和脏位。 当感测到写入数据的请求时，控制单元可以分析对应于数据的地址标签的子线的有效位，基于是否发生高速缓存命中或高速缓存未命中来确定有效位的激活或去激活， 并且执行用于根据所请求数据的大小分配子行的控制操作，并且在发生高速缓存命中时写入数据。