公开(公告)号：US20230185449A1

公开(公告)日：2023-06-15

申请号：US18163943

申请日：2023-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gijae LEE ,  Jebin LEE ,  Sunggu KIM ,  Jiyoung KIM ,  Daehee CHO ,  Hoon CHOI ,  Bumryong HONG ,  Pilwon SEO ,  Jiwoo LEE

IPC: G06F3/04886 ,  G06F1/16

CPC classification number: G06F3/04886 ,  G06F1/1643 ,  G06F1/1683 ,  G06F1/1618

Abstract: At least one processor included in an electronic device can acquire first motion data about the motion of the electronic device through at least one motion sensor, acquire second motion data about a motion of an external device through a connector included in the electronic device, determine, on the basis of the first motion data and the second motion data, the folding angle between the electronic device and the external device connected to the electronic device, and determine, on the basis of the determined folding angle, an input mode that sets whether to display a user interface on a display or whether to block an input signal received through the connector. Various other embodiments identified through the specification are possible.

公开(公告)号：US20230145871A1

公开(公告)日：2023-05-11

申请号：US18093125

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilseub KIM ,  Bomi LEE ,  Pilwon SEO ,  Jiyoung KIM ,  Jiwoo LEE

IPC: G06F3/04847 ,  G06F3/04886 ,  G06F1/16 ,  G06F21/32 ,  G06V40/16

CPC classification number: G06F3/04847 ,  G06F3/04886 ,  G06F1/1624 ,  G06F1/1652 ,  G06F1/1626 ,  G06F21/32 ,  G06V40/172 ,  G06F2203/04803

Abstract: An electronic device is provided, which can include a flexible display, a rolling actuator for expanding or reducing the flexible display, a wireless communication circuit, and a processor. The processor can receive, via the wireless communication circuit, a message from an external device, and in response to receiving the message, drive the first rolling actuator, expand the flexible display by a first length in a first direction, and display a first UI including a plurality of content, in a first region of the flexible display expanded by the first length.

公开(公告)号：US20220392829A1

公开(公告)日：2022-12-08

申请号：US17888727

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung YANG ,  Jiyoung KIM ,  Jiwon KIM

IPC: H01L23/48 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A supporter is on the horizontal conductive layer. The supporter includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection mold layer is between the third portion and the horizontal conductive layer. A first buried insulation layer passing through the third portion, the connection mold layer, and the horizontal conductive layer is provided. A stacked structure is on the substrate. A through electrode passing through the first buried insulation layer is provided.

公开(公告)号：US20220320025A1

公开(公告)日：2022-10-06

申请号：US17529462

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jiyoung KIM ,  Sanghee YOON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device may include a first substrate including a cell array region and a cell array contact region, a peripheral circuit structure on the first substrate, and a cell array structure. The cell array structure may include a stack on the peripheral circuit structure, first vertical channel structures and second vertical channel structures on the cell array region and penetrating the stack, and a second substrate connected to the first vertical channel structures and second vertical channel structures. The stack may be between the peripheral circuit structure and the second substrate. The second substrate may include a first portion and a second portion. The first portion may contact the first vertical channel structures and may be doped a first conductivity type. The second portion may contact the second vertical channel structures and may be doped a second conductivity type different from the first conductivity type.

公开(公告)号：US20220149056A1

公开(公告)日：2022-05-12

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L27/108 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20210035910A1

公开(公告)日：2021-02-04

申请号：US16875174

申请日：2020-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Woosung YANG ,  Jungsok LEE ,  Byungjin LEE

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768

Abstract: A semiconductor memory includes electrode structures that each includes horizontal electrodes stacked on each other a substrate, vertical electrodes between the electrode structures and extending along the horizontal electrodes, first contacts connected to the horizontal electrodes at end portions of the electrode structures, second contacts connected to upper portions of the vertical electrodes, and a first interconnection structure connected to top surfaces of the second contacts. The first interconnection structure includes first and second sub-interconnection lines. The sub-interconnection lines extend in a first direction and contact the top surfaces of the second contacts. The second sub-interconnection lines extended in a second direction crossing the first direction and contact the first sub-interconnection lines.

公开(公告)号：US20180158918A1

公开(公告)日：2018-06-07

申请号：US15868620

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20180151490A1

公开(公告)日：2018-05-31

申请号：US15792911

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin YIM ,  Jongmin BAEK ,  Deokyoung JUNG ,  Kyuhee HAN ,  Byunghee KIM ,  Jiyoung KIM ,  Naein LEE ,  Sangshin JANG

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

公开(公告)号：US20150348459A1

公开(公告)日：2015-12-03

申请号：US14721302

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyung KIM ,  Boram NAMGOONG ,  Yoywang IM ,  Jiyoung KIM ,  Buseop JUNG

IPC: G09G3/20 ,  G06F3/041

CPC classification number: G09G3/2085 ,  A45C11/00 ,  A45C2011/002 ,  A45C2200/10 ,  G06F1/1677 ,  G06F3/0416 ,  G06F3/04886 ,  G06F2200/1634 ,  G06F2203/04107 ,  G09G2310/0213 ,  H04M1/185 ,  H04M1/72575 ,  H04M2250/12

Abstract: A device and methods for content display are disclosed. In various embodiments, a method for content display comprises detecting at least one of an open area or a transparent area in a display cover coupled to an electronic device, setting a partial display-area on a display area of the electronic device in response to the detecting, where the partial display-area corresponds to the at least one of the open area or the transparent area, setting content to the partial display-area, displaying the content in the partial display-area.

Abstract translation: 公开了一种用于内容显示的装置和方法。 在各种实施例中，一种用于内容显示的方法包括检测耦合到电子设备的显示屏幕中的开放区域或透明区域中的至少一个，以响应于所述电子设备的显示区域设置部分显示区域 在所述部分显示区域对应于所述开放区域或所述透明区域中的至少一个的情况下，将所述内容设置为所述部分显示区域，在所述部分显示区域中显示所述内容。

公开(公告)号：US20150303201A1

公开(公告)日：2015-10-22

申请号：US14591165

申请日：2015-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Sungho JANG ,  Jiyoung KIM ,  Kang-Uk KIM ,  Chan Min LEE ,  Juyeon JANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L27/10885 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region.

Abstract translation: 半导体器件及其形成方法包括在基板的单元阵列区域和外围电路区域中形成第一布线膜和蚀刻缓冲膜，并且通过选择性蚀刻蚀刻缓冲膜和第一布线膜形成接触孔 布线膜以暴露电池阵列区域的有源区域和与其相邻的场隔离区域的至少一部分。 在接触孔中形成与有源区接触的位线接触，在基板上形成第二布线膜。 通过图案化第二布线膜，位线接触，蚀刻缓冲膜和第一布线膜，在单元阵列区域中形成位线，并且在外围电路区域中形成周边栅极。