公开(公告)号：US20200212979A1

公开(公告)日：2020-07-02

申请号：US16727391

申请日：2019-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seijoon SHIM ,  Joonho CHO ,  Hayoung YANG ,  Eunae LEE ,  Taejun JANG ,  Jonghwan KIM

IPC: H04B7/06 ,  H04L5/00 ,  H04B7/0417 ,  H04B7/08 ,  H04L27/26

Abstract: A base station for transmitting and receiving signals in a wireless communication system is provided. The base station includes a transceiver, and at least one processor configured to obtain reception antenna weights for the base station including an array of a plurality of antennas, and transmission antenna weights for at least one user equipment (UE), convert signals received from the at least one UE through a plurality of reception paths, into beam-domain signals, based on the transmission antenna weights and the reception antenna weights, combine the converted beam-domain signals by applying predefined combining weights to the converted beam-domain signals, and obtain data from the combined signals.

公开(公告)号：US20160217847A1

公开(公告)日：2016-07-28

申请号：US14966039

申请日：2015-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewoong HA ,  Byungchul KO ,  Daekyoung KIM ,  Jonghwan KIM

IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C7/1045 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2211/4067

Abstract: A memory system including a plurality of dynamic random access memory (DRAM) devices and a DRAM controller is provided. The plurality of DRAM devices includes one or more DRAM groups. Each of the one or more DRAM groups includes at least two DRAM devices. The DRAM controller outputs a clock enable signal, and controls a selection signal used to select a target DRAM device that operates in a normal mode in response to the clock enable signal. At least one target DRAM device is selected from the one or more DRAM groups. One or more stand-by DRAM devices other than the at least one target DRAM device operates in a self-refresh mode.

Abstract translation: 提供了包括多个动态随机存取存储器（DRAM）装置和DRAM控制器的存储器系统。 多个DRAM器件包括一个或多个DRAM组。 一个或多个DRAM组中的每一个包括至少两个DRAM器件。 DRAM控制器输出时钟使能信号，并且响应于时钟使能信号控制用于选择在正常模式下工作的目标DRAM器件的选择信号。 从一个或多个DRAM组中选择至少一个目标DRAM器件。 除了至少一个目标DRAM设备之外的一个或多个备用DRAM设备以自刷新模式工作。