Abstract:
Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.
Abstract:
Provided is a ferroelectric semiconductor device including a source and a drain having different polarities. The ferroelectric semiconductor may include a ferroelectric including zirconium oxide (ZrO2), hafnium oxide (HfO2), and/or hafnium-zirconium oxide (HfxZr1−xO, 0
Abstract:
A thin film structure including ferroelectrics and anti-ferroelectrics and a semiconductor device including the same are provided. The thin film structure includes a first anti-ferroelectric layer comprising anti-ferroelectrics, a second anti-ferroelectric layer disposed apart from the first anti-ferroelectric layer and including anti-ferroelectrics, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric layer and including ferroelectrics.
Abstract:
A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.
Abstract:
A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.
Abstract:
A semiconductor device, a memory device, and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a semiconductor substrate, a ferroelectric layer provided on the semiconductor substrate, an aluminum oxide layer provided on the ferroelectric layer, and a gate electrode provided on the aluminum oxide layer, wherein the aluminum oxide layer includes aluminum, oxygen, and hydrogen, and wherein a content of oxygen in the aluminum oxide layer is more than about 1.5 times and about 2 times or less a content of aluminum in the aluminum oxide layer.
Abstract:
Provided is a ferroelectric field effect transistor including a source region, a drain region, a channel provided between the source region and the drain region, a ferroelectric layer provided on the channel and including a ferroelectric material including an oxide of a first element, a gate-interposed layer provided on the ferroelectric layer and including a paraelectric material including an oxide of a second element different from the first element, and a gate electrode provided on the gate-interposed layer, wherein the gate-interposed layer includes a first interposed layer adjacent to the ferroelectric layer, and a second interposed layer adjacent to the gate electrode, the first interposed layer includes a mixture of the first element and the second element, and a ratio of the first element in the first interposed layer may be greater than a ratio of the first element in the ferroelectric layer.
Abstract:
Provided is a semiconductor device including a ferroelectric layer. The semiconductor device includes a channel layer including an n-type oxide semiconductor layer and a p-type oxide semiconductor layer, a ferroelectric layer disposed on the channel layer, a gate electrode disposed on the ferroelectric layer, and a reduced layer disposed on the channel layer and including an element having greater reducing power than a metal included in the channel layer.
Abstract:
A semiconductor device including a substrate, an interfacial layer on the substrate, a ferroelectric layer on the interfacial layer, a gate on the ferroelectric layer, and the nitride protective layer between the interfacial layer and the gate and being adjacent to the ferroelectric layer.
Abstract:
A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.