公开(公告)号：US20080278193A1

公开(公告)日：2008-11-13

申请号：US12219213

申请日：2008-07-17

Applicant: Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

Inventor： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/017545

Abstract: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

公开(公告)号：US07400541B2

公开(公告)日：2008-07-15

申请号：US11863604

申请日：2007-09-28

Applicant: Seong-Jin Jang ,  Jeong-Don Lim

Inventor： Seong-Jin Jang ,  Jeong-Don Lim

IPC: G11C7/06

CPC classification number: G11C7/1006 ,  G06F7/501 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C2207/108

Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.

Abstract translation: 数据总线反转（DBI）电路包括至少一个DBI块，其被配置为基于输入数据位的逻辑状态反转输入数据信号。 DBI块包括比较判定单元，该比较判定单元被配置为通过比较输入数据信号和先前输入数据信号的各个比特信号，在第一模式中，基于改变的比特数来生成比较信号。 比较判定单元生成控制输入数据是否反转的反转控制信号。 在第二模式中，比较判定单元根据输入数据信号位的主要逻辑状态生成反转控制信号。 数据转换单元被配置为响应于反转控制信号来反转输入数据信号。 还公开了方法实施例。

公开(公告)号：US20080144406A1

公开(公告)日：2008-06-19

申请号：US12071347

申请日：2008-02-20

Applicant: Kwang-ll Park ,  Seong-Jin Jang ,  Ho-Young Song

Inventor： Kwang-ll Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

Abstract: An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

Abstract translation: 输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控​​制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。 一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。

公开(公告)号：US20070229320A1

公开(公告)日：2007-10-04

申请号：US11693264

申请日：2007-03-29

Applicant: Seung-Jun Bae ,  Seong-Jin Jang

Inventor： Seung-Jun Bae ,  Seong-Jin Jang

IPC: H03M7/00

CPC classification number: H03M5/145

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract translation: 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US07237073B2

公开(公告)日：2007-06-26

申请号：US10737861

申请日：2003-12-18

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G06F5/00 ,  G06F13/00 ,  G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1096

Abstract: A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

Abstract translation: 存储器系统和将数据读取和写入存储器件的方法提供逐字节写入数据插入，而不会向封装器件添加额外的引脚或球。 因此，可以提高装置的高频性能。

公开(公告)号：US07092299B2

公开(公告)日：2006-08-15

申请号：US10792623

申请日：2004-03-03

Applicant: Jin-Seok Kwak ,  Seong-Jin Jang ,  Young-Hyun Jun

Inventor： Jin-Seok Kwak ,  Seong-Jin Jang ,  Young-Hyun Jun

IPC: G11C7/00

CPC classification number: G11C5/063 ,  G11C7/10 ,  G11C7/1048

Abstract: A memory system includes first and second memory devices having commonly connected data terminals and commonly connected memory control signal terminals, e.g., devices in respective first and second independently selectable memory banks that share common data lines and common memory control signal lines, such as column address strobe, row address strobe, write enable, and address signal lines. The first and second memory devices includes respective selective on-die termination (ODT) circuits configured to selectively provide first and second termination impedances at their respective data terminals responsive to a memory control signal at the commonly connected memory control signal terminals. The selective ODT circuits may produce the first termination impedance responsive to a memory write operation, and may produce the second termination impedance responsive to a memory read operation and/or expiration of a predetermined time interval following termination of the memory write operation. Preferably, the first termination impedance is less than the second termination impedance, and the selective ODT circuits provide the first termination impedance responsive to the memory write operation irrespective of which of the first and second memory devices is being written to.

Abstract translation: 存储器系统包括具有共同连接的数据端子和共同连接的存储器控​​制信号端子的第一和第二存储器件，例如共享公共数据线和公共存储器控制信号线的各自的第一和第二可独立选择的存储体中的器件，诸如列地址 选通，行地址选通，写使能和地址信号线。 第一和第二存储器件包括相应的选择性管芯端接（ODT）电路，其被配置为响应于在共同连接的存储器控​​制信号端子处的存储器控​​制信号在它们各自的数据端口选择性地提供第一和第二终端阻抗。 响应于存储器写入操作，选择性ODT电路可以产生第一终止阻抗，并且可以在存储器写入操作终止之后响应于存储器读取操作和/或预定时间间隔的期满而产生第二终止阻抗。 优选地，第一终端阻抗小于第二终端阻抗，并且选择性ODT电路响应于存储器写入操作提供第一终止阻抗，而与正在写入的第一和第二存储器件中的哪一个无关。

公开(公告)号：US20060060986A1

公开(公告)日：2006-03-23

申请号：US11229257

申请日：2005-09-16

Applicant: Sung-Hoon Kim ,  Young-Chul Cho ,  Kwang-Il Park ,  Seong-Jin Jang

Inventor： Sung-Hoon Kim ,  Young-Chul Cho ,  Kwang-Il Park ,  Seong-Jin Jang

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

公开(公告)号：US20060038577A1

公开(公告)日：2006-02-23

申请号：US11191376

申请日：2005-07-28

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G01R31/02

CPC classification number: G05F3/02 ,  G11C5/147

Abstract: A circuit for generating a reference voltage includes a first reference voltage generating circuit disposed outside a chip and a second reference voltage generating circuit disposed inside the chip. The first and second reference voltage generating circuits output first and second reference voltages to first and second output terminals, respectively. The second reference voltage generating circuit includes at least one pull-up resistor and at least one pull-down resistor. The pull-up resistor is coupled between a first node where an internal power supply voltage is coupled and the second output terminal. The pull-down resistor is coupled between a second node and the second output terminal, wherein a voltage at the second node is relatively lower than a voltage at the first node. A third reference voltage is outputted from a node where the first output terminal is coupled to the second output terminal.

公开(公告)号：US20050068840A1

公开(公告)日：2005-03-31

申请号：US10943514

申请日：2004-09-17

Applicant: Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

Inventor： Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

IPC: G11C11/407 ,  G11C8/02 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4063

CPC classification number: G11C8/12

Abstract: A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.

Abstract translation: 用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段 行地址。 还公开了相关设备。

公开(公告)号：US06801067B2

公开(公告)日：2004-10-05

申请号：US10404102

申请日：2003-04-02

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: H03H1126

CPC classification number: H03K5/135 ,  H03K5/13 ,  H03L7/08

Abstract: A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits, The ASMD circuit may include a comparator with first and second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal, and a second precharge circuit connected to the second input terminal and precharging the second input terminal. The ASMD circuit may also include a first pair of discharge circuits discharging the first input terminal within first and second cycles of the input clock, and a second pair of discharge circuits discharging the second input terminal within first and second cycles of the input clock.

Abstract translation: 产生时钟的方法可以使用具有占空比校正方案的模拟同步镜延迟（ASMD）电路，并且内部时钟发生器可以使用一个或多个ASMD电路.ASMD电路可以包括比较器，其具有第一和第二 输入端子，其基于第一输入端子上的信号与第二输入端子上的信号之间的比较结果产生输出时钟;第一预充电电路，连接到第一输入端子并对第一输入端子进行预充电;以及第二预充电 电路连接到第二输入端并对第二输入端子进行预充电。 ASMD电路还可以包括在输入时钟的第一和第二周期内对第一输入端子进行放电的第一对放电电路，以及在输入时钟的第一和第二周期内对第二输入端子进行放电的第二对放电电路。