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    RECEIVER WITH FREQUENCY DEVIATION DETECTION CAPABILITY AND METHOD THEREFOR
    31.
    发明申请
    RECEIVER WITH FREQUENCY DEVIATION DETECTION CAPABILITY AND METHOD THEREFOR 审中-公开
    具有频偏偏差检测能力的接收机及其方法

    公开(公告)号：US20150092586A1

    公开(公告)日：2015-04-02

    申请号：US14500382

    申请日：2014-09-29

    Applicant: Silicon Laboratories Inc.

    Inventor： Hendricus de Ruijter ,  Wentao Li

    IPC: H04W24/08 ,  H04L27/12 ,  H04L27/10

    CPC classification number: H04W24/08 ,  H04L27/106 ,  H04L27/12 ,  H04L27/148

    Abstract: A receiver includes an analog receiver and a digital processor. The analog receiver has an input for receiving a radio frequency (RF) signal, and an output for providing a digital intermediate frequency signal. The digital processor has an input for receiving the digital intermediate frequency signal, and an output for providing digital symbols. The digital processor measures peak-to-peak frequency deviation of the digital intermediate frequency signal, and performs a digital signal processing function on the digital intermediate frequency signal to provide the digital symbols based on the peak-to-peak frequency deviation so measured.

    Abstract translation: 接收机包括模拟接收机和数字处理器。 模拟接收机具有用于接收射频（RF）信号的输入端和用于提供数字中频信号的输出端。 数字处理器具有用于接收数字中频信号的输入端和用于提供数字符号的输出端。 数字处理器测量数字中频信号的峰 - 峰频偏，并对数字中频信号执行数字信号处理功能，以便根据如此测量的峰 - 峰频偏提供数字符号。

    NON-COHERENT DSSS DEMODULATOR WITH FAST SIGNAL ARRIVAL DETECTION AND IMPROVED TIMING AND FREQUENCY OFFSET ESTIMATION
    32.
    发明申请
    NON-COHERENT DSSS DEMODULATOR WITH FAST SIGNAL ARRIVAL DETECTION AND IMPROVED TIMING AND FREQUENCY OFFSET ESTIMATION 有权

    公开(公告)号：US20250007769A1

    公开(公告)日：2025-01-02

    申请号：US18217015

    申请日：2023-06-30

    Applicant: Silicon Laboratories Inc.

    Inventor： Wentao Li ,  Yan Zhou ,  Terry Lee Dickey

    IPC: H04L27/26 ,  H04L5/00 ,  H04L25/497

    Abstract: A receiver includes a demodulator having a configurable correlator bank that helps with fast and robust signal detection. The demodulator detects arrival of a first preamble symbol using a first correlator bank configuration. The demodulator makes a course frequency offset estimation after detection of the first preamble signal and the receiver adjusts a frequency used by a mixer based on the coarse frequency offset estimation. The demodulator confirms signal arrival detection with detection of a second preamble symbol. A coarse timing estimation is generated using a second correlator bank configuration using a multi-symbol observation period. A fine frequency offset estimation is made using a third correlation bank configuration. A fine timing estimation is made using a fourth correlation bank configuration. The demodulator then despreads received symbols using a fifth correlator bank configuration.

    CONCURRENT LISTENING
    33.
    发明公开
    CONCURRENT LISTENING 审中-公开

    公开(公告)号：US20230371067A1

    公开(公告)日：2023-11-16

    申请号：US17743042

    申请日：2022-05-12

    Applicant: Silicon Laboratories Inc.

    Inventor： Terry L. Dickey ,  Yan Zhou ,  Wentao Li ,  Rangakrishnan Srinivasan

    IPC: H04W74/08 ,  H04W74/04 ,  H04L5/00 ,  H04W4/80 ,  H04W4/23

    CPC classification number: H04W74/0808 ,  H04W74/04 ,  H04L5/0053 ,  H04W4/80 ,  H04W4/23

    Abstract: A wireless communication device has a receiver to listen to a sequence of channels. A controller responds to a preamble being detected on a first channel while the receiver is tuned to the first channel by causing the receiver to stay on the first channel and decode packet(s) associated with the preamble. The controller responds to detection of a first symbol of a first transmission protocol and the preamble not being detected to cause the receiver to stay on the first channel for a predetermined time waiting for a retry. The controller responds to detection of a second symbol of a second transmission protocol and the preamble not being detected to cause the receiver to switch to an advertising channel of the second transmission protocol. If no preambles, noise, or symbols are detected, the receiver switches to listening to a next channel in the sequence after a fixed time.

    Adjusting receiver frequency to compensate for frequency offset during a sounding sequence used for fractional time determination
    35.
    发明授权
    Adjusting receiver frequency to compensate for frequency offset during a sounding sequence used for fractional time determination 有权

    公开(公告)号：US11502883B2

    公开(公告)日：2022-11-15

    申请号：US17108912

    申请日：2020-12-01

    Applicant: Silicon Laboratories Inc.

    Inventor： Wentao Li ,  Michael A. Wu ,  Yan Zhou

    IPC: H04L27/00 ,  H04L27/14

    Abstract: A mixer in a receiver converts a sounding sequence of alternating ones and zeros to an intermediate frequency signal. A digital mixer converts the intermediate frequency signal to a baseband signal that contains a positive tone and a negative tone. A frequency offset correction circuit generates frequency offset corrections based on frequency offset estimates of the frequency offset between a transmitter of the sounding sequence and the receiver. A frequency adjustment circuit adjusts a frequency of the mixer or the digital mixer to thereby center the positive tone and the negative tone around DC. DFT circuits perform single bin DFTs respectively centered on the positive and negative tones. Phases of the positive and negative tones are calculated based on outputs of the DFT circuits and the phases are used to determine fractional time value associated with a distance measurement between the transmitter and receiver.

    ADJUSTING DFT COEFFICIENTS TO COMPENSATE FOR FREQUENCY OFFSET DURING A SOUNDING SEQUENCE USED FOR FRACTIONAL TIME DETERMINATION
    36.
    发明申请
    ADJUSTING DFT COEFFICIENTS TO COMPENSATE FOR FREQUENCY OFFSET DURING A SOUNDING SEQUENCE USED FOR FRACTIONAL TIME DETERMINATION 有权

    公开(公告)号：US20220174453A1

    公开(公告)日：2022-06-02

    申请号：US17108908

    申请日：2020-12-01

    Applicant: Silicon Laboratories Inc.

    Inventor： Wentao Li ,  Yan Zhou ,  Michael A. Wu

    IPC: H04W4/02 ,  G01S11/02 ,  H04L12/26 ,  G01R23/175

    Abstract: A receiver includes a first discrete Fourier transform (DFT) block to perform a first single tone DFT on a positive tone associated with a sounding sequence. A second DFT block performs a second single tone DFT on a negative tone associated with the sounding sequence. A DFT coefficient generation block generates first DFT coefficients based on a nominal frequency of the positive tone and an estimated frequency offset between a transmitter frequency and a receiver frequency. The DFT coefficient generation block generates second DFT coefficients based on a nominal frequency of the negative tone and the estimated frequency offset. Multipliers in the DFT blocks multiply I and Q values of the sounding sequence with the coefficients. Accumulators in the DFT blocks accumulate multiplier outputs. An arctan function receives averaged accumulated values from the first and second DFT blocks and supplies first and second phase values used to calculate fractional timing.

    System and method of operating automatic gain control in the presence of high peak-to-average ratio blockers
    39.
    发明授权
    System and method of operating automatic gain control in the presence of high peak-to-average ratio blockers 有权

    公开(公告)号：US10742185B1

    公开(公告)日：2020-08-11

    申请号：US16367908

    申请日：2019-03-28

    Applicant: Silicon Laboratories Inc.

    Inventor： Wentao Li ,  Guner Arslan ,  Yan Zhou

    IPC: H03G3/30 ,  H04L27/26 ,  H04B1/18 ,  H03F3/189 ,  H03M1/12 ,  H03F1/26

    Abstract: A wireless receiver including a gain network that adjusts a gain of a received wireless signal and provides an RF signal, a level detector that provides a level indication while a strength of the RF signal is at least an RF level threshold, a timing system that provides a timing value indicative of a total amount of time that the level indication is provided during a timing window, a gain up disable circuit that provides a gain up disable signal when the timing value reaches a low threshold, a blocker strength detect circuit that provides a gain down request signal when the timing value reaches a high threshold, and an AGC circuit that does not increase the gain of the gain network while the gain up disable signal is provided, and that allows a reduction of the gain of the gain network while the gain down request signal is provided.

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