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公开(公告)号：US20180234107A1
公开(公告)日：2018-08-16
申请号：US15950690
申请日：2018-04-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jagannathan Venkataraman , Prabu Sankar Thirugnanam , Raja Reddy Patukuri , Sandeep Kesrimal Oswal
IPC: H03M3/00
Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.
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公开(公告)号：US20150305648A1
公开(公告)日：2015-10-29
申请号：US14694500
申请日：2015-04-23
Applicant: Texas Instruments Incorporated
Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source that generates an excitation signal. A switched resistor network is coupled to the excitation source, and generates an output signal in response to the excitation signal. A sense circuit is coupled to the switched resistor network, and generates a sense signal in response to the output signal. A comparator is coupled to the sense circuit, and generates a clock signal in response to the sense signal. A mixer is coupled to the sense circuit, and multiplies the sense signal and the clock signal to generate a rectified signal. A low pass filter is coupled to the mixer and filters the rectified signal to generate an averaged signal. A processor is coupled to the low pass filter and measures a body impedance from the averaged signal.
Abstract translation: 本公开提供了一种用于阻抗测量的电路。 该电路包括产生激励信号的激励源。 开关电阻网络耦合到激励源，并且响应于激励信号产生输出信号。 感测电路耦合到开关电阻网络，并且响应于输出信号产生感测信号。 比较器耦合到感测电路，并响应于感测信号产生时钟信号。 混频器耦合到感测电路，并且将感测信号和时钟信号相乘以产生整流信号。 低通滤波器耦合到混频器并对整流信号进行滤波以产生平均信号。 处理器耦合到低通滤波器并根据平均信号测量身体阻抗。
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33.发明申请公开(公告)号：US20150256151A1
公开(公告)日：2015-09-10
申请号：US14640175
申请日：2015-03-06
Applicant: Texas Instruments Incorporated
Inventor： Rahul Sharma , Vajeed Nimran , Jagannathan Venkataraman , Sandeep Kesrimal Oswal
CPC classification number: H03H19/004 , A61B6/032 , A61B6/4208 , G01T1/17 , H02J7/345 , H03H11/1291
Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.
Abstract translation: 本公开提供了一种电路，其包括响应于当前信号产生积分信号的积分器。 比较器耦合到积分器并接收积分信号和主参考电压信号。 比较器产生反馈信号。 开关电容网络跨越积分器耦合。 反馈信号激活开关电容网络。
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公开(公告)号：US11641216B2
公开(公告)日：2023-05-02
申请号：US17689627
申请日：2022-03-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sarma Sundareswara Gunturi , Jagannathan Venkataraman , Jawaharlal Tangudu , Narasimhan Rajagopal , Eeshan Miglani
Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.
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公开(公告)号：US20230054834A1
公开(公告)日：2023-02-23
申请号：US17567775
申请日：2022-01-03
Applicant: Texas Instruments Incorporated
Inventor： Rakesh Manjunath , Aravind Ganesan , Ani Xavier , Jagannathan Venkataraman , Abhishek Agrawal , Charls Babu , Aditya Kumar
Abstract: A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.
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Patent Agency Ranking
公开(公告)号：US11416021B2
公开(公告)日：2022-08-16
申请号：US17245711
申请日：2021-04-30
Applicant: Texas Instruments Incorporated
Inventor： Ani Xavier , Jagannathan Venkataraman , Raviteja Velisetti
Abstract: A first logic gate has a first input coupled to a first circuit input or a second circuit input, a second input selectively coupled to a third circuit input or a fourth circuit input, and a first output. The first output has a signal with a duty cycle that is a function of a phase difference between a first signal on the first input and a second signal on the second input. A second logic gate has a third input coupled to the third circuit input or the fourth circuit input, a fourth input coupled to the second circuit input or the fourth circuit input, and a second output. The second output has a signal with a duty cycle that is a function of a phase difference between a third signal on the third input and a fourth signal on the fourth input.
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公开(公告)号：US20220182266A1
公开(公告)日：2022-06-09
申请号：US17363855
申请日：2021-06-30
Applicant: Texas Instruments Incorporated
Inventor： Ani Xavier , Jagannathan Venkataraman , Nagalinga Swamy Basayya Aremallapur , Aviral Singhal , Arun Mohan , Rakesh Chikkanayakanahalli Manjunath , Aravind Ganesan , Harshavardhan Adepu
Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.
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公开(公告)号：US10930362B2
公开(公告)日：2021-02-23
申请号：US16916911
申请日：2020-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aravind Ganesan , Jaiganesh Balakrishnan , Nagarajan Viswanathan , Yeswanth Guntupalli , Ajai Paulose , Mathews John , Jagannathan Venkataraman , Neeraj Shrivastava
Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.
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公开(公告)号：US10911161B2
公开(公告)日：2021-02-02
申请号：US16697236
申请日：2019-11-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Oswal , Visvesvaraya Pentakota , Jagannathan Venkataraman , Jaiganesh Balakrishnan , Francesco Dantoni
Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.
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公开(公告)号：US10795002B2
公开(公告)日：2020-10-06
申请号：US16128040
申请日：2018-09-11
Applicant: Texas Instruments Incorporated
Inventor： Jagannathan Venkataraman
Abstract: The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.
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