公开(公告)号：US20170263696A1

公开(公告)日：2017-09-14

申请号：US15606158

申请日：2017-05-26

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L23/5225 ,  H01L27/0629 ,  H01L28/00 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US09583558B2

公开(公告)日：2017-02-28

申请号：US15045421

申请日：2016-02-17

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract translation: 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。

公开(公告)号：US20160172434A1

公开(公告)日：2016-06-16

申请号：US15045421

申请日：2016-02-17

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US20240113096A1

公开(公告)日：2024-04-04

申请号：US18149099

申请日：2022-12-31

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Yoshihiro Takei ,  Mitsuhiro Sugimoto

IPC: H01L27/01

CPC classification number: H01L27/016

Abstract: A microelectronic device includes a lower isolation element and an upper isolation element, separated by an isolation dielectric layer stack. The microelectronic device includes a lower field reduction layer over the lower isolation element, under the isolation dielectric layer stack. The lower field reduction layer includes a first dielectric layer adjacent to the isolation dielectric layer stack, and a second dielectric layer over the first dielectric layer. A dielectric constant of the first dielectric layer is greater than a dielectric constant of the second dielectric layer. The dielectric constant of the second dielectric layer is greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer. Methods of forming example microelectronic device having lower field reduction layers are disclosed.

公开(公告)号：US20240113042A1

公开(公告)日：2024-04-04

申请号：US17958040

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield ,  Toshiyuki Tamura ,  Yoshihiro Takei

IPC: H01L23/58 ,  H01L21/762 ,  H01L23/00 ,  H01L23/532 ,  H01L23/544

CPC classification number: H01L23/585 ,  H01L21/762 ,  H01L23/53295 ,  H01L23/544 ,  H01L24/06 ,  H01L2223/54426 ,  H01L2224/04042 ,  H01L2224/06102

Abstract: A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

公开(公告)号：US11901402B2

公开(公告)日：2024-02-13

申请号：US17529750

申请日：2021-11-18

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/49575 ,  H01L24/05 ,  H01L25/16 ,  H01L2224/0556 ,  H01L2224/05624

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

公开(公告)号：US20230420489A1

公开(公告)日：2023-12-28

申请号：US18242717

申请日：2023-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01G4/005 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0292

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

公开(公告)号：US20230154974A1

公开(公告)日：2023-05-18

申请号：US17529750

申请日：2021-11-18

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L23/00 ,  H01L25/16 ,  H01L23/495

CPC classification number: H01L28/60 ,  H01L24/05 ,  H01L25/16 ,  H01L23/49575 ,  H01L2224/0556 ,  H01L2224/05624

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

公开(公告)号：US11495553B2

公开(公告)日：2022-11-08

申请号：US16526765

申请日：2019-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01L23/64 ,  H01L27/07 ,  H01L23/00 ,  H01L49/02 ,  B81B7/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/495

Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

公开(公告)号：US20220208956A1

公开(公告)日：2022-06-30

申请号：US17138059

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West

IPC: H01L49/02

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.