公开(公告)号：US20230253489A1

公开(公告)日：2023-08-10

申请号：US18134582

申请日：2023-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, where the surface of the semiconductor barrier layer includes at least one recess. The gate electrode is disposed on the semiconductor barrier layer and includes a body portion and at least one vertical extension portion overlapping the recess.

公开(公告)号：US11721697B2

公开(公告)日：2023-08-08

申请号：US17735114

申请日：2022-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Yu-Wen Hung

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356

Abstract: A manufacturing method of a semiconductor device is provided in an embodiment of the present invention. The manufacturing method includes the following steps. A transistor is formed on a substrate. The transistor includes a plurality of semiconductor sheets and two source/drain structures. The semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the two first doped layers. The two source/drain structures are disposed at two opposite sides of each of the semiconductor sheets in a horizontal direction respectively, and the two source/drain structures are connected with the semiconductor sheets.

公开(公告)号：US11462636B2

公开(公告)日：2022-10-04

申请号：US17197075

申请日：2021-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US20220223724A1

公开(公告)日：2022-07-14

申请号：US17185979

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, where the surface of the semiconductor barrier layer includes at least one recess. The gate electrode is disposed on the semiconductor barrier layer and includes a body portion and at least one vertical extension portion overlapping the recess.

公开(公告)号：US20220216167A1

公开(公告)日：2022-07-07

申请号：US17160332

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/00

Abstract: A hybrid bonding structure includes a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive layer. A first barrier surrounds the first conductive layer. A first air gap surrounds and contacts the first barrier. A first dielectric layer surrounds and contacts the first air gap. The second conductive structure includes a second conductive layer. A second barrier contacts the second conductive layer. A second dielectric layer surrounds the second barrier. The second conductive layer bonds to the first conductive layer. The first dielectric layer bonds to the second dielectric layer.

公开(公告)号：US20220172992A1

公开(公告)日：2022-06-02

申请号：US17137298

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/78 ,  H01L23/544

Abstract: A manufacturing method of a semiconductor device includes the following steps. A singulation process is performed to a semiconductor wafer for forming semiconductor dies and includes a first cutting step, a thinning step, and a second cutting step. The first cutting step is configured to form first openings in the semiconductor wafer by etching. A portion of the semiconductor wafer is located between each first opening and a back surface and removed by the thinning step. Each first opening penetrates through the semiconductor wafer after the thinning step. The second cutting step is configured to form second openings. Each second opening penetrates through the semiconductor wafer for separating the semiconductor dies. A semiconductor die includes two first side surfaces opposite to each other and two second side surfaces opposite to each other. A roughness of each first side surface is different from a roughness of each second side surface.

公开(公告)号：US20220130956A1

公开(公告)日：2022-04-28

申请号：US17079552

申请日：2020-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/06 ,  H01L29/24 ,  H01L21/322 ,  H01L29/34 ,  H01L29/10 ,  H01L27/12

Abstract: A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.

公开(公告)号：US20220093593A1

公开(公告)日：2022-03-24

申请号：US17083342

申请日：2020-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/822

Abstract: A semiconductor device includes a substrate, a first transistor and a second transistor disposed on the substrate, and a first contact structure. The first transistor includes first semiconductor channel layers stacked and separated from one another, and a first source/drain structure and a second source/drain structure disposed at two opposite sides of and connected with each first semiconductor channel layer. The second transistor includes second semiconductor channel layers disposed above the first semiconductor channel layers, stacked, and separated from one another, and a third source/drain structure and a fourth source/drain structure disposed at two opposite sides of and connected with each second semiconductor channel layer. The first contact structure penetrates through the third source/drain structure. The first source/drain structure is electrically connected with the third source/drain structure via the first contact structure, and a part of the first source/drain structure is disposed between the substrate and the first contact structure.

公开(公告)号：US10903362B2

公开(公告)日：2021-01-26

申请号：US16260158

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/033 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/10

Abstract: A semiconductor device includes a substrate having an upper surface; a source region in the substrate; a drain region in the substrate and spaced apart from the source region; a channel region between the source region and the drain region; a gate structure on the channel region; m dislocations in the source region, wherein m is an integer greater than or equal to 1; and n dislocations in the drain region, wherein n is an integer greater than or equal to 0, and wherein m is greater than n.

公开(公告)号：US09627544B2

公开(公告)日：2017-04-18

申请号：US14817577

申请日：2015-08-04

Applicant: United Microelectronics Corp.

Inventor： Po-Yu Yang

IPC: H01L29/775 ,  H01L21/84 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/78684 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a semiconductor device is disclosed. At least one suspended first semiconductor nanowire and two first semiconductor blocks at two ends of the first semiconductor nanowire are formed in a first area, and at least one suspended second semiconductor nanowire and two second semiconductor blocks at two ends of the second semiconductor nanowire are formed in a second area. A transforming process is performed, so the first semiconductor nanowire is transformed into a nanowire with stress, and the second semiconductor blocks are simultaneously transformed into two blocks with stress. First and second gate dielectric layers are formed respectively on surfaces of the nanowire with stress and the second semiconductor nanowire. First and second gates are formed respectively across the nanowire with stress and the second semiconductor nanowire.