公开(公告)号：US09379128B1

公开(公告)日：2016-06-28

申请号：US14809342

申请日：2015-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Wen-Peng Hsu

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L21/225

CPC classification number: H01L27/11568 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

Abstract translation: 分路门NVM器件包括半导体衬底，设置在半导体衬底上的ONO结构，设置在ONO结构上的第一栅电极，设置在半导体衬底上的第二栅极，与第一栅电极相邻并绝缘， ONO结构，在半导体衬底中形成并与ONO结构相邻的具有第一导电性的第一掺杂区，在半导体衬底中形成并与第二栅电极相邻的具有第一导电性的第二掺杂区，以及第三掺杂区， 所述第一导电体形成在所述半导体衬底中，设置在所述第一掺杂区域和所述第二掺杂区域之间并且邻近所述ONO结构和所述第二栅电极。